HEART 2014 Design Contest: Tools & Boards
Tools: the test & host program
Test & host program is available. (Download May.28 version)
- Developed on FreeBSD 8.3 (amd64). Should work on any POSIX based systems (with small modifications around serial port communications.)
- Works on Cygwin (serial_dev may be have to modified).
- On other platforms,
- modify /dev entries in serial_dev
- init_serial() may be have to be modified
- PATCHES FOR OTHER PLATFORM ARE WELCOME!
Command line options:
- Game modes: Human (on stdin) and FPGA board (on serial port)
can be either First move player or second move player. To play
in human vs human mode, simply running without any options.
- No option: Player 1/2 on console: Human vs human.
- -1: Player 1 on serial port 0: FPGA board moves first, then human.
- -2: Player 1 on serial port 0: Human moves first, then FPGA board.
- -3: Player 1/2 on serial port 0/1: FPGA board vs FPGA board.
- -r: reverse serial port assignment on '-3' option.
- Hint options for test:
- -t: Do NOT show list of available tiles.
- -p: Show the shape of placed tile.
- -h: Show hint: but usually not a good move :p
- -a : Simple AI plays instead of human on stdin. "-a 1" moves as "-h" option, and "-a 2" moves a little bit wiser than that.
- Communication options:
- -T: Opens TCP port 10000 (and 10001) as a replacement of serial port 0 (and 1).
- -o XX: Set serial port timeout to XX second(s).
To interrupt this program in interactive mode, press Ctrl+D (not Ctrl+C). This will transmit "9" to the serial port to make the game over.
The Web interface: blokus-httpd
May.01 version of the Test & Host program contains "blokus-httpd.c", which is an Web-based viewer of blokus-host. To use it, simply launch as:
./blokus-host | ./blokus-httpd
Then connect http://localhost:11000/ on your browser and start the game as on the console, serial or TCP.
To use blokus-httpd, do not give "hint options" to blokus-host. Any other options about game modes and communication are allowed.
Known issues / restrictions
- On Cygwin, serial port setup should be done by setup_com12.bat before running blokus-host.
- Only 1 browser session is allowed on a blokus-httpd.
- Internet connection is required (or modify the HTML source to use jQuery on your local directory.)
- The browser must support HTML5 Canvas.
- "blokus.html" must be in current directory.
- May.28, 2014:
- Jan.10, 2014:
- Initial version.
- Yasunori Osana <email@example.com> wrote this file.
- This file is provided "AS IS" in the Beerware license rev 42.
- Prof. Akira Kojima @ Hiroshima City University provided the "-a 2" option, cygwin compatibility and batch-file for serial port setup (setup_com12.bat).
- Many Blokus Duo challengers has reported bugs. Thank you for all contributors.
Updated: Jan.29, 2014
The following list gives approved FPGA boards. Boards with smaller FPGAs and external RAM capacities are also allowed to get involved.
The boards will communicate with the host via D-sub 9pin RS-232C interface. Also, FTDI's USB-UART controller chips (such as on Digilent boards) are allowed in the competition.
- Altera DE2 Boards (with Cyclone II EP2C35, EP2C70 or Cyclone IV EP4CE115)
- Digilent Nexys4 (with Artix-7 XC7A100T)
- Digilent Atlys (with SPARTAN-6 XC6LX45)
- Xilinx Virtex-5 evaluation platform (ML509, with Virtex-5 XC5VLX110T)
- Xilinx Spartan 3E starter / development board
- Xilinx Virtex-II Pro Development System (use of embedded PowerPC is not allowed)
- Xilinx XtremeDSP starter platform (with Spartan-3 DSP 1800A)
Other FPGA Boards
Participating with other FPGA boards is also allowed if:
- The FPGA on the board is one of the list below.
- No hard IP microprocessor core is active in the design.
- Total off-chip memory utilization is less than 256MB (except the configuration bitstream). Any types of external memory (ROMs, SRAMs, DRAMs, DIMMs etc.) is allowed within the 256MB limit.
- The board has D-sub 9pin RS-232C interface, or FTDI's USB -UART controller.
Note: To participate with boards with hard IP microprocessor core or 256MB+ memory, a part of the design source code (where the memory capacity is explicitly limited, for example, by tying down several address lines) MUST be sent to the competition chair. The submission of source code is only for regulation compliance check, and will not be disclosed. For simpleness of the compliance check, please send ONLY the modules that limits memory capacity.
List of approved FPGAs
FPGAs in the following list and smaller devices in the lines are approved in the 2014 competition (updated: Jan.29, 2014.)
- Altera Stratix
- Stratix III: EP3SE150, EP3SL150
- Stratix II: EP2S130
- Stratix: All devices
- Altera Arria
- Arria II : EP2AGX125
- Arria: All devices
- Altera Cyclone
- Cyclone V: EP5CEA5, EP5CGXC5, EP5CGTD5, EP5CSEA5, EP5CSXC5, EP5CSTD5
- Cyclone IV: All devices
- Cyclone III: EP3CLS150, EP3C120
- Cyclone II: All devices
- Cyclone: All devices
- Xilinx Virtex
- Virtex-5: XC5VLX155(T), XC5VSX95T, XC5VFX130T, XC5VTX150T
- Virtex-4: XC4VLX160, XC4VSX55, XC4VFX140
- Virtex-II Pro: All devices
- Virtex-II: All devices
- Virtex-E: All devices
- Virtex: All devices
- Xilinx Artix
- Artix-7: XC7A35T, XC7A50T, XC7A75T, XC7A100T
- Xilinx Spartan
- Spartan-6: XC6SLX75(T)
- Spartan-3A/AN/E: All devices
- Spartan-II/IIE: All devices