ICFPT 2013 Blokus Duo Competition: Tools & Boards

Tools: the test & host program

Test & host program is available. (Download Nov.27 version)

Platform

• Developed on FreeBSD 8.3 (amd64). Should work on any POSIX based systems (with small modifications around serial port communications.)
• Works on Cygwin (serial_dev[] may be have to modified).
• On other platforms,
  • modify /dev entries in serial_dev[]
  • init_serial() may be have to be modified
• PATCHES FOR OTHER PLATFORM ARE WELCOME!

Command line options:

• Game modes: Human (on stdin) and FPGA board (on serial port) can be either First move player or second move player. To play in human vs human mode, simply running without any options.
  • No option: Player 1/2 on console: Human vs human.
  • -1: Player 1 on serial port 0: FPGA board moves first, then human.
  • -2: Player 1 on serial port 0: Human moves first, then FPGA board.
  • -3: Player 1/2 on serial port 0/1: FPGA board vs FPGA board.
  • -r: reverse serial port assignment on '-3' option.
• Hint options for test:
  • -t: Do NOT show list of available tiles.
  • -p: Show the shape of placed tile.
  • -h: Show hint: but usually not a good move :p
  • -a [12]: Simple AI plays instead of human on stdin. "-a 1" moves as "-h" option, and "-a 2" moves a little bit wiser than that.
• Communication options:
  • -T: Opens TCP port 10000 (and 10001) as a replacement of serial port 0 (and 1).
  • -o XX: Set serial port timeout to XX second(s).

To interrupt this program in interactive mode, press Ctrl+D (not Ctrl+C). This will transmit "9" to the serial port to make the game over.

The Web interface: blokus-httpd

May.01 version of the Test & Host program contains "blokus-httpd.c", which is an Web-based viewer of blokus-host. To use it, simply launch as:

./blokus-host | ./blokus-httpd

Then connect http://localhost:11000/ on your browser and start the game as on the console, serial or TCP.

To use blokus-httpd, do not give "hint options" to blokus-host. Any other options about game modes and communication are allowed.

Known issues / restrictions

• blokus-host:
  • On Cygwin, serial port setup should be done by setup_com12.bat before running blokus-host.
• blokus-httpd:
  • Only 1 browser session is allowed on a blokus-httpd.
  • Internet connection is required (or modify the HTML source to use jQuery on your local directory.)
  • The browser must support HTML5 Canvas.
  • "blokus.html" must be in current directory.

Revision history

Show/Hide older news

• Oct.08, 2013:
  • Team ID displayed with -2 option fixed.
• Sep.27, 2013:
  • -a [12] option (simple software player) added for automated test.
• Sep.11, 2013:
  • blokus-httpd generates log file for replay.
  • For replay, try 'echo cat 00XX-XX-XX.log | ./blokus-httpd'.
• Aug.14, 2013:
  • Fixed code "9" comes with 9 bytes of garbage.

• Jul.26, 2013:
  • cfsetispeed() + cfsetospeed() fix. Previous versions couldn't correctly set serial port speed to 115200bps on some platforms.
  • Transmits code "9" only 1 time at the end of the match. Previous versions had 10 times, like "9999999999".
• May.14, 2013:
  • Proper HTTP handling to improve Linux / Cygwin compatibility.
• May.07, 2013:
  • Improved web interface.
  • blokus-httpd terminates correctly when the game is over.
• May.01, 2013:
  • Web-based interface provided by blokus-httpd.
  • Timeout support bugfixes.
• Apr.11, 2013:
  • Timeout support.
  • FPGA vs FPGA mode support.
• Apr.10, 2013:
  • Invalid code on serial port results in immediate loss of game.
  • First/second moves are restricted on (5,5) and (a,a), respectively.
  • Game terminates when both make pass by theirselves.
  • '-T' option to communicate via TCP, insetead of serial I/O.
  • Ignores CR/LF characters to make tests easy.
  • '-r' option to make player 2 first.
• Apr.02, 2013:
  • Fixed 'p' tile (important!)
  • Players can pass anytime after first move.
  • Small bugfixes.
• Mar.26, 2013:
  • Follow-up to Protocol 0.9.
• Mar.19, 2013:
  • Fixed to comply the communication protocol (FPGA sends 4-letter code XXXX, but not 3XXXX!).
  • Removed test code (that occupies some grids at start).
• Mar.13, 2013: Requires "0000" to pass on serial port (automatically pass on stdin). Proper EOF handling on stdin.
• Mar.12, 2013: First version released.

License

• Yasunori Osana <osana@eee.u-ryukyu.ac.jp> wrote this file.
• This file is provided "AS IS" in the Beerware license rev 42.

Acknowlegements

• Prof. Akira Kojima @ Hiroshima City University provided the "-a 2" option, cygwin compatibility and batch-file for serial port setup (setup_com12.bat).
• Many Blokus Duo challengers has reported bugs. Thank you for all contributors.

Boards

The following list gives approved FPGA boards. Boards with smaller FPGAs and external RAM capacities are also allowed to get involved.

The boards will communicate with the host via D-sub 9pin RS-232C interface. Also, FTDI's USB-UART controller chips (such as on Digilent boards) are allowed in the competition.

• Altera DE2 Boards (with Cyclone II EP2C35, EP2C70 or Cyclone IV EP4CE115)
• Digilent Atlys (with SPARTAN-6 XC6LX45)
• Xilinx Spartan 3E starter / development board
• Xilinx Virtex-II Pro Development System (use of embedded PowerPC is not allowed)
• Xilinx XtremeDSP starter platform (with Spartan-3 DSP 1800A)

Other FPGA Boards

Participating with other FPGA boards is also allowed if:

• The FPGA on the board is one of the list below.
• No hard IP microprocessor core is active in the design.
• Total off-chip memory utilization is less than 256MB (except the configuration bitstream). Any types of external memory (ROMs, SRAMs, DRAMs, DIMMs etc.) is allowed within the 256MB limit.
• The board has D-sub 9pin RS-232C interface, or FTDI's USB-UART controller.

Note: To participate with boards with hard IP microprocessor core or 256MB+ memory, a part of the design source code (where the memory capacity is explicitly limited, for example, by tying down several address lines) MUST be sent to the competition chair. The submission of source code is only for regulation compliance check, and will not be disclosed. For simpleness of the compliance check, please send ONLY the modules that limits memory capacity.

List of approved FPGAs

FPGAs in the following list and smaller devices in the lines are approved in the 2013 competition.

• Altera Stratix
  • Stratix III: EP3SE110, EP3SL110
  • Stratix II: EP2S130
  • Stratix: EP1S80
• Altera Arria
  • Arria II : EP2AGX125
  • Arria: All devices
• Altera Cyclone
  • Cyclone V: EP5CEA5, EP5CGXC5, EP5CGTD5, EP5CSEA5, EP5CSXC5, EP5CSTD5
  • Cyclone IV: All devices
  • Cyclone III: EP3CL100, EP3C120
  • Cyclone II: All devices
  • Cyclone: All devices
• Xilinx Virtex
  • Virtex-5: XC5VLX50(T), XC5VSX35T, XC5VFX30T
  • Virtex-4: XC4VLX80, XC4VSX35, XC4VFX20
  • Virtex-II Pro: XC2VP50
  • Virtex-II: XC2V8000
  • Virtex-E: All devices
  • Virtex: All devices
• Xilinx Spartan
  • Spartan-6: XC6SLX75(T)
  • Spartan-3A/AN/E: All devices
  • Spartan-II/IIE: All devices