ICFPT 2013 Design Competition: Blokus Duo
- Game logs from Pre-finals and Finals are now available in Resources.
- Nov.27: Test & host update in Tools & Boards. Now your team codes are embedded.
- Oct.27: Here is the list of competitors!
- Oct.08: Test & host update in Tools & Boards.
- Oct.08: A new page for Competitors is now available.
- Oct.06: Our server may go down due to coming Typhoon. It'll be stable again on Oct.08.
- Oct.02: Submission is now closed. All competitors should read Final checklist. Test & host update in Tools & Boards.
- Sep.20: DEADLINE EXTENSION: Contest paper / abstract submission is extended to SEP.30,2013.
- Sep.11: Test & host update in Tools & Boards. Terminate code fix, etc.
- Sep.11: We're planning a poster session on competition designs.
- Aug.22: Entry/submission is now open! The "Getting Involved" section of this page has a major update.
- Aug.14: Test & host update in Tools & Boards. Terminate code fix, etc.
- May.14: Test & host update in Tools & Boards. Linux/Cygwin compatibility fix.
- May.07: The competition entry schedule has been announced.
- May.01: iLink LLC and Impulse Accelerated Technologies offers license of Impulse C/CoDeveloper tools to competition challengers.
- May.07: Test & host update in Tools & Boards. Improved Web interface.
- May.01: Test & host update in Tools & Boards. Web-based interface is available!
- Apr.11: Test & host update in Tools & Boards. Now supports FPGA vs FPGA mode!
- Apr.10: Test & host update in Tools & Boards.
- Apr.02: Test & host IMPORTANT update in Tools & Boards
- Mar.26: Test & host update in Tools & Boards (now compatible with protocol 0.9!)
- Mar.20: Communication protocol update (Pre-final: version 0.9) in Rules.
- Mar.19: Test & host update in Tools & Boards.
- Mar.13: Test & host update in Tools & Boards.
- Mar.12: Test & host program is available in Tools & Boards.
- Feb.12: Detailed list of boards/FPGAs in Tools & Boards.
- Jan.17: Communication protocol (preliminary: version 0.0) in Rules.
- Dec.17: Description of the four-letter code in Rules.
- Dec.11: Competition website open.
Following on the successful Connect6 competitions, we'll compete against each other at a game called Blokus Duo with our FPGA implementations, at ICFPT 2013.
Blokus Duo is a two-player game played on a square, 14x14 grid board. Each player has 21 different-shaped game tiles. Each new piece played must be placed to contact at least one piece of the same color with their corner-to-corner. Edge-to-edge contact is only allowed to the other color.
The competition has finished successfully. Thanks to all competitors and audience. Replay movies will be on this website, soon.
- Pre-competition check: Dec.08 morning (by the "Final Checklist" protocol above)
- Pre-Finals: Dec.08 afternoon (All 26 teams in 4 leagues)
- Finals: Dec.11 afternoon (8 teams in 1 league: best 2 teams from each league)
8 best teams from 21 teams in the pre-finals:
- 1st: FPGA Blokus Duo Solver
- 2nd: R-BULLET
- 3rd: DohiBlokus
- 4th: University of Zaragoza, ERTL
- 6th: Liquid Metal
- 7th: Reconfigurable Application Diffusion Committee
- 8th: HATARAKU FPGA SAMA! second season
List of All Competitors
|Mt.Cape||fc.ritsumei.ac.jp||YA||Impulse C + Verilog HDL / Impulse + Altera Quartus II|
|Chester||ntu.edu.tw||CH||Verilog HDL / Altera Quartus II|
|FANTEK (withdrawn)||kiau.ac.ir||FA||Verilog HDL / ?|
|LegUp High-Level Synthesis||toronto.edu||LU||C / LegUp HLS|
|TNT (withdrawn)||titech.ac.jp||TN||Verilog HDL / Xilinx ISE|
|Clemson (no show)||clemson.edu||CL||Impulse C + Verilog HDL / Impulse C + Altera Quartus II|
|Liquid Metal||ibm.com||LM||Lime / Liquid Meta + Xilinx ISE|
|ERTL||ertl.jp||ER||C + VHDL / eXCite + Altera Quartus II|
|TUC-Blokus (no show)||tuc.gr||TU|
|i-coma||naist.jp||IC||Verilog HDL / Altera Quartus II|
|A.B.C.||tohoku.ac.jp||TP||Verilog HDL / Altera Quartus II|
|R-BULLET||ritsumei.ac.jp||RB||Impulse C / Altera Quartus II|
|Pulse-R B2||ritsumei.ac.jp||PR||Impulse C / Altera Quartus II|
|FPGA Blokus Duo Solver||shizuoka.ac.jp||BD||VHDL / Altera Quartus II|
|Block Boiler||tohtech.ac.jp||TS||Verilog HDL / Altra Quartus II|
|HATARAKU FPGA SAMA! second season||keio.ac.jp||HF||Cyber WorkBench / Xilinx ISE|
|University of Zaragoza||unizar.es||UZ||VHDL / Xilinx ISE|
|DohiBlokus||nagasaki-u.ac.jp||DB||Verilog HDL / Altera Quartus II|
|Kuma 2 Duo||kumamoto-u.ac.jp||KU||Verilog HDL / Altera Quartus II|
|SAKURA-Duo||nagasaki-u.ac.jp||SD||Verilog HDL / Altera Quartus II|
|Reconfigurable Application Diffusion Committee||hiroshima-cu.ac.jp||RA||Verilog HDL / Xilinx ISE|
|Okayama University||okayama-u.ac.jp||OU||SFL + Verilog-HDL/ PARTHENON + Altera Quartus II|
|LILA.CS||tsukuba.ac.jp||LI||Verilog HDL / Xilinx ISE|
Entry / submission has been closed.
- a competition paper (that describes your competition FPGA design) within 4 pages
- or 1 page abstract of your competition design
from ICFPT 2013 Submission webpage. Either must follow the ICFPT 2013 paper template. Additionally, the there's a plan of a poster session on the competition designs (details depend on the number of entries).
Competition papers will be reviewed by the program committees who will not attend at the competition, and will appear on the proceedings if accepted. Even if your competition paper has been rejected, you still are a competitor at ICFPT 2013.
The best designs will be selected to go through a live competition in the ICFPT 2013.
- Competition paper submission / Entry deadline: Sep.30, 2013.
- Notification: Oct.14, 2013.
- Camera-ready due: Oct.30, 2013.
Competition chair(s) may contact the competitors by E-mail, to collect supplemental information about the design.
- Competition chair:
- Yasunori Osana (University of the Ryukyus) <osana at eee.u-ryukyu.ac.jp>.
- Competition Committees:
- Eiko Sugawara (Akita National College of Technology)
- Hiroki Nakahara (Kagoshima University)
- Hironori Nakajo (Tokyo University of Agriculture and Technology)
- Jubee Tada (Yamagata University)
- Shinya Takamaeda-Yamazaki (Tokyo Institute of Technology)
- Yasutaka Wada (The University of Electro-Communications)