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// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename:			cross_domain_signal.v
// Version:				1.00.a
// Verilog Standard:	Verilog-2001
// Description:			Send a signal from clock domain A into clock domain B
// and get the signal back into clock domain A. Domain A can know roughly when 
// the signal is received domain B. 
// Author:				Matt Jacobsen
// History:				@mattj: Version 2.0
//-----------------------------------------------------------------------------

`timescale 1ns/1ns
module cross_domain_signal (
	input CLK_A,		// Clock for domain A
	input CLK_A_SEND,	// Signal from domain A to domain B
	output CLK_A_RECV,	// Signal from domain B received in domain A 
	input CLK_B,		// Clock for domain B
	output CLK_B_RECV,	// Signal from domain A received in domain B
	input CLK_B_SEND	// Signal from domain B to domain A
);


// Sync level signals across domains.
syncff sigAtoB (.CLK(CLK_B), .IN_ASYNC(CLK_A_SEND), .OUT_SYNC(CLK_B_RECV));
syncff sigBtoA (.CLK(CLK_A), .IN_ASYNC(CLK_B_SEND), .OUT_SYNC(CLK_A_RECV));


endmodule