xilinx.com xci unknown 1.0 fifo_128x512_64_afull 100000000 0 0.000 100000000 0 0.000 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 100000000 0 0.000 100000000 0 0.000 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 100000000 0 0.000 0 0 0 0 0 0 0 8 1 1 1 1 4 0 32 1 1 1 64 1 8 1 1 1 1 1 0 9 BlankString 128 1 32 64 1 64 2 0 64 0 1 0 0 0 0 0 0 0 0 kintexu 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 1 1 0 0 1 BlankString 1 0 0 0 1 0 512x72 1kx18 512x36 512x72 512x36 512x72 512x36 2 1022 1022 1022 1022 1022 1022 3 0 0 0 0 0 0 0 410 1023 1023 1023 1023 1023 1023 409 1 0 0 0 0 0 0 0 0 11 1024 1 10 0 0 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 10 512 1024 16 1024 16 1024 16 1 9 10 4 10 4 10 4 1 32 0 0 false false false 0 0 Slave_Interface_Clock_Enable Common_Clock fifo_128x512_64_afull 64 false 9 false false 0 2 1022 1022 1022 1022 1022 1022 3 false false false false false false false false false Hard_ECC false false false false false false true false false true Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM 0 410 1023 1023 1023 1023 1023 1023 409 false false false 0 Native false false false false false false false false false false false false false false 128 512 1024 16 1024 16 1024 16 false 64 1024 Embedded_Reg false false Active_High Active_High AXI4 Standard_FIFO No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold Single_Programmable_Full_Threshold_Constant No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold READ_WRITE 0 1 false 11 Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered true Synchronous_Reset false 1 0 0 1 1 4 false false Active_High Active_High true false false true true Active_High 0 false Active_High 1 false 10 true FIFO false false false false FIFO FIFO 2 2 false FIFO FIFO FIFO kintexu xcku115 flvb2104 VERILOG VERILOG -2 E TRUE TRUE IP_Flow 3 TRUE . . 2018.3 OUT_OF_CONTEXT