Intel Corporation pr_ip alt_pr_0 19.1.0 clk clk clk clockRate Clock rate 0 externallyDriven Externally driven false ptfSchematicName PTF schematic name nreset reset_n nreset associatedClock Associated clock clk synchronousEdges Synchronous edges DEASSERT pr_start pr_start pr_start associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false double_pr double_pr double_pr associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false freeze freeze freeze associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false status status status associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false avst_sink data data valid data_valid ready data_ready associatedClock associatedClock clk associatedReset associatedReset nreset beatsPerCycle Beats Per Cycle 1 dataBitsPerSymbol Data bits per symbol 32 emptyWithinPacket emptyWithinPacket false errorDescriptor Error descriptor firstSymbolInHighOrderBits First Symbol In High-Order Bits true highOrderSymbolAtMSB highOrderSymbolAtMSB false maxChannel Maximum channel 0 packetDescription Packet description prSafe Partial Reconfiguration Safe false readyAllowance Ready allowance 0 readyLatency Ready latency 0 symbolsPerBeat Symbols per beat 1 QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH alt_pr QUARTUS_SYNTH clk in STD_LOGIC QUARTUS_SYNTH nreset in STD_LOGIC QUARTUS_SYNTH pr_start in STD_LOGIC QUARTUS_SYNTH double_pr in STD_LOGIC QUARTUS_SYNTH freeze out STD_LOGIC QUARTUS_SYNTH status out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH data in 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH data_valid in STD_LOGIC QUARTUS_SYNTH data_ready out STD_LOGIC QUARTUS_SYNTH Intel Corporation pr_ip alt_pr 19.1.0 PR_INTERNAL_HOST Use as partial reconfiguration internal host true ENABLE_JTAG Enable JTAG debug mode true ENABLE_AVMM_SLAVE Enable Avalon-MM slave interface false ENABLE_INTERRUPT Enable interrupt interface false ENABLE_FREEZE Enable freeze interface true ENABLE_HPR_UI Enable hierarchical PR support false ENABLE_HPR ENABLE_HPR false ENABLE_PRPOF_ID_CHECK_UI Enable bitstream compatibility check false ENABLE_PRPOF_ID_CHECK ENABLE_PRPOF_ID_CHECK true EXT_HOST_PRPOF_ID PR bitstream ID 0 EXT_HOST_TARGET_DEVICE_FAMILY Target device family for external host Arria 10 DATA_WIDTH_INDEX Input data width 32 CB_DATA_WIDTH CB_DATA_WIDTH 16 ENABLE_DATA_PACKING ENABLE_DATA_PACKING true CDRATIO Clock-to-data ratio 1 EDCRC_OSC_DIVIDER Divide error detection frequency by 1 ENABLE_ENHANCED_DECOMPRESSION Enable enhanced decompression false INSTANTIATE_PR_BLOCK Auto-instantiate partial reconfiguration control block true INSTANTIATE_CRC_BLOCK Auto-instantiate CRC block true DEVICE_FAMILY DEVICE_FAMILY Cyclone 10 GX GENERATE_SDC Generate timing constraints file true device Device 10CX220YF780E5G deviceFamily Device family Cyclone 10 GX deviceSpeedGrade Device Speed Grade 5 generationId Generation Id 0 bonusData bonusData bonusData { element alt_pr_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> false false