Intel Corporation icap_dcm iopll_0 19.3.0 reset reset rst associatedClock Associated clock synchronousEdges Synchronous edges NONE ui.blockdiagram.direction input refclk clk refclk clockRate Clock rate 100000000 externallyDriven Externally driven false ptfSchematicName PTF schematic name ui.blockdiagram.direction input locked export locked associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output outclk0 clk outclk_0 associatedDirectClock Associated direct clock clockRate Clock rate 33333333 clockRateKnown Clock rate known true externallyDriven Externally driven false ptfSchematicName PTF schematic name ui.blockdiagram.direction output QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH altera_iopll QUARTUS_SYNTH rst in STD_LOGIC QUARTUS_SYNTH refclk in STD_LOGIC QUARTUS_SYNTH locked out STD_LOGIC QUARTUS_SYNTH outclk_0 out STD_LOGIC QUARTUS_SYNTH Intel Corporation icap_dcm altera_iopll 19.3.0 gui_device_family Device Family Cyclone 10 GX gui_device_component Component 10CX220YF780E5G gui_device_speed_grade Speed Grade 5 gui_debug_mode false gui_skip_sdc_generation false gui_include_iossm false gui_cal_code_hex_file iossm.hex gui_parameter_table_hex_file seq_params_sim.hex gui_pll_tclk_mux_en false gui_pll_tclk_sel pll_tclk_m_src gui_pll_vco_freq_band_0 pll_freq_clk0_disabled gui_pll_vco_freq_band_1 pll_freq_clk1_disabled gui_pll_freqcal_en true gui_pll_freqcal_req_flag true gui_cal_converge false gui_cal_error cal_clean gui_pll_cal_done false gui_pll_type S10_Simple gui_pll_m_cnt_in_src c_m_cnt_in_src_ph_mux_clk gui_c_cnt_in_src0 c_m_cnt_in_src_ph_mux_clk gui_c_cnt_in_src1 c_m_cnt_in_src_ph_mux_clk gui_c_cnt_in_src2 c_m_cnt_in_src_ph_mux_clk gui_c_cnt_in_src3 c_m_cnt_in_src_ph_mux_clk gui_c_cnt_in_src4 c_m_cnt_in_src_ph_mux_clk gui_c_cnt_in_src5 c_m_cnt_in_src_ph_mux_clk gui_c_cnt_in_src6 c_m_cnt_in_src_ph_mux_clk gui_c_cnt_in_src7 c_m_cnt_in_src_ph_mux_clk gui_c_cnt_in_src8 c_m_cnt_in_src_ph_mux_clk system_info_device_family Device Family Cyclone 10 GX system_info_device_component Component 10CX220YF780E5G system_info_device_speed_grade Speed Grade 5 system_part_trait_speed_grade Speed Grade Trait 5 gui_usr_device_speed_grade Speed Grade 1 gui_en_reconf Enable dynamic reconfiguration of PLL false gui_en_dps_ports Enable access to dynamic phase shift ports false gui_pll_mode PLL Mode Integer-N PLL gui_location_type IOPLL Type I/O Bank gui_use_logical Use logical PLL false gui_reference_clock_frequency Reference Clock Frequency 100.0 gui_reference_clock_frequency_ps Reference Clock Frequency 10000.0 gui_use_coreclk Refclk source is global clock false gui_refclk_might_change My reference clock frequency might change false gui_fractional_cout Fractional carry out 32 gui_prot_mode prot_mode UNUSED gui_dsm_out_sel DSM Order 1st_order gui_use_locked Enable locked output port true gui_en_adv_params Enable physical output clock parameters false gui_pll_bandwidth_preset PLL Bandwidth Preset Low gui_lock_setting Lock Threshold Setting Low Lock Time gui_pll_auto_reset PLL Auto Reset false gui_en_lvds_ports Access to PLL LVDS_CLK/LOADEN output port Disabled gui_operation_mode Compensation Mode direct gui_feedback_clock Feedback Clock Global Clock gui_clock_to_compensate Compensated Outclk 0 gui_use_NDFB_modes Use Nondedicated Feedback Path false gui_refclk_switch Create a second input clock signal 'refclk1' false gui_refclk1_frequency Second Reference Clock Frequency 100.0 gui_en_phout_ports Enable access to PLL DPA output port false gui_phout_division PLL DPA output division 1 gui_en_extclkout_ports Enable access to PLL external clock output port false gui_number_of_clocks Number Of Clocks 1 gui_multiply_factor Multiply Factor (M-Counter) 6 gui_divide_factor_n Divide Factor (N-Counter) 1 gui_frac_multiply_factor Fractional Multiply Factor (K) 1 gui_fix_vco_frequency Specify VCO frequency false gui_fixed_vco_frequency Desired VCO Frequency 600.0 gui_fixed_vco_frequency_ps Desired VCO Frequency 1667.0 gui_vco_frequency Actual VCO Frequency 600.0 gui_enable_output_counter_cascading Enable output counter cascading false gui_mif_gen_options MIF Generation Options Generate New MIF File gui_new_mif_file_path Path to New MIF file ~/pll.mif gui_existing_mif_file_path Path to Existing MIF file ~/pll.mif gui_mif_config_name Name of Current Configuration unnamed gui_active_clk Create an 'active_clk' signal to indicate the input clock in use false gui_clk_bad Create a 'clkbad' signal for each of the input clocks false gui_switchover_mode Switchover Mode Automatic Switchover gui_switchover_delay Switchover Delay 0 gui_enable_cascade_out Create a 'cascade_out' signal to connect to a downstream PLL false gui_cascade_outclk_index cascade_out source 0 gui_enable_cascade_in Create an 'adjpllin' (cascade in) signal to connect to an upstream PLL through IO Column Cascading false gui_enable_permit_cal Connect to an upstream PLL through Core Clock Network Cascading (create a permit_cal input signal) false gui_pll_cascading_mode Connection Signal Type to Upstream PLL adjpllin gui_enable_mif_dps Enable Dynamic Phase Shift for MIF streaming false gui_dps_cntr DPS Counter Selection C0 gui_dps_num Number of Dynamic Phase Shifts 1 gui_dps_dir Dynamic Phase Shift Direction Positive gui_extclkout_0_source extclk_out[0] source C0 gui_extclkout_1_source extclk_out[1] source C0 gui_clock_name_global Give clocks global names false gui_clock_name_string0 Clock Name clk33 gui_clock_name_string1 Clock Name outclk1 gui_clock_name_string2 Clock Name outclk2 gui_clock_name_string3 Clock Name outclk3 gui_clock_name_string4 Clock Name outclk4 gui_clock_name_string5 Clock Name outclk5 gui_clock_name_string6 Clock Name outclk6 gui_clock_name_string7 Clock Name outclk7 gui_clock_name_string8 Clock Name outclk8 gui_clock_name_string9 Clock Name outclk9 gui_clock_name_string10 Clock Name outclk10 gui_clock_name_string11 Clock Name outclk11 gui_clock_name_string12 Clock Name outclk12 gui_clock_name_string13 Clock Name outclk13 gui_clock_name_string14 Clock Name outclk14 gui_clock_name_string15 Clock Name outclk15 gui_clock_name_string16 Clock Name outclk16 gui_clock_name_string17 Clock Name outclk17 gui_divide_factor_c0 Divide Factor (C-Counter) 6 gui_divide_factor_c1 Divide Factor (C-Counter) 6 gui_divide_factor_c2 Divide Factor (C-Counter) 6 gui_divide_factor_c3 Divide Factor (C-Counter) 6 gui_divide_factor_c4 Divide Factor (C-Counter) 6 gui_divide_factor_c5 Divide Factor (C-Counter) 6 gui_divide_factor_c6 Divide Factor (C-Counter) 6 gui_divide_factor_c7 Divide Factor (C-Counter) 6 gui_divide_factor_c8 Divide Factor (C-Counter) 6 gui_divide_factor_c9 Divide Factor (C-Counter) 6 gui_divide_factor_c10 Divide Factor (C-Counter) 6 gui_divide_factor_c11 Divide Factor (C-Counter) 6 gui_divide_factor_c12 Divide Factor (C-Counter) 6 gui_divide_factor_c13 Divide Factor (C-Counter) 6 gui_divide_factor_c14 Divide Factor (C-Counter) 6 gui_divide_factor_c15 Divide Factor (C-Counter) 6 gui_divide_factor_c16 Divide Factor (C-Counter) 6 gui_divide_factor_c17 Divide Factor (C-Counter) 6 gui_cascade_counter0 Make this a cascade counter false gui_cascade_counter1 Make this a cascade counter false gui_cascade_counter2 Make this a cascade counter false gui_cascade_counter3 Make this a cascade counter false gui_cascade_counter4 Make this a cascade counter false gui_cascade_counter5 Make this a cascade counter false gui_cascade_counter6 Make this a cascade counter false gui_cascade_counter7 Make this a cascade counter false gui_cascade_counter8 Make this a cascade counter false gui_cascade_counter9 Make this a cascade counter false gui_cascade_counter10 Make this a cascade counter false gui_cascade_counter11 Make this a cascade counter false gui_cascade_counter12 Make this a cascade counter false gui_cascade_counter13 Make this a cascade counter false gui_cascade_counter14 Make this a cascade counter false gui_cascade_counter15 Make this a cascade counter false gui_cascade_counter16 Make this a cascade counter false gui_cascade_counter17 Make this a cascade counter false gui_output_clock_frequency0 Desired Frequency 33.333333 gui_output_clock_frequency1 Desired Frequency 100.0 gui_output_clock_frequency2 Desired Frequency 100.0 gui_output_clock_frequency3 Desired Frequency 100.0 gui_output_clock_frequency4 Desired Frequency 100.0 gui_output_clock_frequency5 Desired Frequency 100.0 gui_output_clock_frequency6 Desired Frequency 100.0 gui_output_clock_frequency7 Desired Frequency 100.0 gui_output_clock_frequency8 Desired Frequency 100.0 gui_output_clock_frequency9 Desired Frequency 100.0 gui_output_clock_frequency10 Desired Frequency 100.0 gui_output_clock_frequency11 Desired Frequency 100.0 gui_output_clock_frequency12 Desired Frequency 100.0 gui_output_clock_frequency13 Desired Frequency 100.0 gui_output_clock_frequency14 Desired Frequency 100.0 gui_output_clock_frequency15 Desired Frequency 100.0 gui_output_clock_frequency16 Desired Frequency 100.0 gui_output_clock_frequency17 Desired Frequency 100.0 gui_output_clock_frequency_ps0 Desired Frequency 30000.0 gui_output_clock_frequency_ps1 Desired Frequency 10000.0 gui_output_clock_frequency_ps2 Desired Frequency 10000.0 gui_output_clock_frequency_ps3 Desired Frequency 10000.0 gui_output_clock_frequency_ps4 Desired Frequency 10000.0 gui_output_clock_frequency_ps5 Desired Frequency 10000.0 gui_output_clock_frequency_ps6 Desired Frequency 10000.0 gui_output_clock_frequency_ps7 Desired Frequency 10000.0 gui_output_clock_frequency_ps8 Desired Frequency 10000.0 gui_output_clock_frequency_ps9 Desired Frequency 10000.0 gui_output_clock_frequency_ps10 Desired Frequency 10000.0 gui_output_clock_frequency_ps11 Desired Frequency 10000.0 gui_output_clock_frequency_ps12 Desired Frequency 10000.0 gui_output_clock_frequency_ps13 Desired Frequency 10000.0 gui_output_clock_frequency_ps14 Desired Frequency 10000.0 gui_output_clock_frequency_ps15 Desired Frequency 10000.0 gui_output_clock_frequency_ps16 Desired Frequency 10000.0 gui_output_clock_frequency_ps17 Desired Frequency 10000.0 gui_actual_output_clock_frequency0 Actual Frequency 33.333333 gui_actual_output_clock_frequency1 Actual Frequency 100.0 gui_actual_output_clock_frequency2 Actual Frequency 100.0 gui_actual_output_clock_frequency3 Actual Frequency 100.0 gui_actual_output_clock_frequency4 Actual Frequency 100.0 gui_actual_output_clock_frequency5 Actual Frequency 100.0 gui_actual_output_clock_frequency6 Actual Frequency 100.0 gui_actual_output_clock_frequency7 Actual Frequency 100.0 gui_actual_output_clock_frequency8 Actual Frequency 100.0 gui_actual_output_clock_frequency9 Actual Frequency 100.0 gui_actual_output_clock_frequency10 Actual Frequency 100.0 gui_actual_output_clock_frequency11 Actual Frequency 100.0 gui_actual_output_clock_frequency12 Actual Frequency 100.0 gui_actual_output_clock_frequency13 Actual Frequency 100.0 gui_actual_output_clock_frequency14 Actual Frequency 100.0 gui_actual_output_clock_frequency15 Actual Frequency 100.0 gui_actual_output_clock_frequency16 Actual Frequency 100.0 gui_actual_output_clock_frequency17 Actual Frequency 100.0 gui_actual_output_clock_frequency_range0 Legal Frequencies 33.243243,33.25,33.255814,33.333333,33.414634,33.421053 gui_actual_output_clock_frequency_range1 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range2 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range3 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range4 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range5 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range6 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range7 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range8 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range9 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range10 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range11 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range12 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range13 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range14 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range15 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range16 Legal Frequencies 100.0 gui_actual_output_clock_frequency_range17 Legal Frequencies 100.0 gui_ps_units0 Phase Shift Units ps gui_ps_units1 Phase Shift Units ps gui_ps_units2 Phase Shift Units ps gui_ps_units3 Phase Shift Units ps gui_ps_units4 Phase Shift Units ps gui_ps_units5 Phase Shift Units ps gui_ps_units6 Phase Shift Units ps gui_ps_units7 Phase Shift Units ps gui_ps_units8 Phase Shift Units ps gui_ps_units9 Phase Shift Units ps gui_ps_units10 Phase Shift Units ps gui_ps_units11 Phase Shift Units ps gui_ps_units12 Phase Shift Units ps gui_ps_units13 Phase Shift Units ps gui_ps_units14 Phase Shift Units ps gui_ps_units15 Phase Shift Units ps gui_ps_units16 Phase Shift Units ps gui_ps_units17 Phase Shift Units ps gui_phase_shift0 Desired Phase Shift 0.0 gui_phase_shift1 Desired Phase Shift 0.0 gui_phase_shift2 Desired Phase Shift 0.0 gui_phase_shift3 Desired Phase Shift 0.0 gui_phase_shift4 Desired Phase Shift 0.0 gui_phase_shift5 Desired Phase Shift 0.0 gui_phase_shift6 Desired Phase Shift 0.0 gui_phase_shift7 Desired Phase Shift 0.0 gui_phase_shift8 Desired Phase Shift 0.0 gui_phase_shift9 Desired Phase Shift 0.0 gui_phase_shift10 Desired Phase Shift 0.0 gui_phase_shift11 Desired Phase Shift 0.0 gui_phase_shift12 Desired Phase Shift 0.0 gui_phase_shift13 Desired Phase Shift 0.0 gui_phase_shift14 Desired Phase Shift 0.0 gui_phase_shift15 Desired Phase Shift 0.0 gui_phase_shift16 Desired Phase Shift 0.0 gui_phase_shift17 Desired Phase Shift 0.0 gui_phase_shift_deg0 Desired Phase Shift 0.0 gui_phase_shift_deg1 Desired Phase Shift 0.0 gui_phase_shift_deg2 Desired Phase Shift 0.0 gui_phase_shift_deg3 Desired Phase Shift 0.0 gui_phase_shift_deg4 Desired Phase Shift 0.0 gui_phase_shift_deg5 Desired Phase Shift 0.0 gui_phase_shift_deg6 Desired Phase Shift 0.0 gui_phase_shift_deg7 Desired Phase Shift 0.0 gui_phase_shift_deg8 Desired Phase Shift 0.0 gui_phase_shift_deg9 Desired Phase Shift 0.0 gui_phase_shift_deg10 Desired Phase Shift 0.0 gui_phase_shift_deg11 Desired Phase Shift 0.0 gui_phase_shift_deg12 Desired Phase Shift 0.0 gui_phase_shift_deg13 Desired Phase Shift 0.0 gui_phase_shift_deg14 Desired Phase Shift 0.0 gui_phase_shift_deg15 Desired Phase Shift 0.0 gui_phase_shift_deg16 Desired Phase Shift 0.0 gui_phase_shift_deg17 Desired Phase Shift 0.0 gui_actual_phase_shift0 Actual phase shift 0.0 gui_actual_phase_shift1 Actual phase shift 0.0 gui_actual_phase_shift2 Actual phase shift 0.0 gui_actual_phase_shift3 Actual phase shift 0.0 gui_actual_phase_shift4 Actual phase shift 0.0 gui_actual_phase_shift5 Actual phase shift 0.0 gui_actual_phase_shift6 Actual phase shift 0.0 gui_actual_phase_shift7 Actual phase shift 0.0 gui_actual_phase_shift8 Actual phase shift 0.0 gui_actual_phase_shift9 Actual phase shift 0.0 gui_actual_phase_shift10 Actual phase shift 0.0 gui_actual_phase_shift11 Actual phase shift 0.0 gui_actual_phase_shift12 Actual phase shift 0.0 gui_actual_phase_shift13 Actual phase shift 0.0 gui_actual_phase_shift14 Actual phase shift 0.0 gui_actual_phase_shift15 Actual phase shift 0.0 gui_actual_phase_shift16 Actual phase shift 0.0 gui_actual_phase_shift17 Actual phase shift 0.0 gui_actual_phase_shift_range0 Legal Phase Shifts 0.0,87.2,89.3,91.5,93.8,96.2 gui_actual_phase_shift_range1 Legal Phase Shifts 0.0 gui_actual_phase_shift_range2 Legal Phase Shifts 0.0 gui_actual_phase_shift_range3 Legal Phase Shifts 0.0 gui_actual_phase_shift_range4 Legal Phase Shifts 0.0 gui_actual_phase_shift_range5 Legal Phase Shifts 0.0 gui_actual_phase_shift_range6 Legal Phase Shifts 0.0 gui_actual_phase_shift_range7 Legal Phase Shifts 0.0 gui_actual_phase_shift_range8 Legal Phase Shifts 0.0 gui_actual_phase_shift_range9 Legal Phase Shifts 0.0 gui_actual_phase_shift_range10 Legal Phase Shifts 0.0 gui_actual_phase_shift_range11 Legal Phase Shifts 0.0 gui_actual_phase_shift_range12 Legal Phase Shifts 0.0 gui_actual_phase_shift_range13 Legal Phase Shifts 0.0 gui_actual_phase_shift_range14 Legal Phase Shifts 0.0 gui_actual_phase_shift_range15 Legal Phase Shifts 0.0 gui_actual_phase_shift_range16 Legal Phase Shifts 0.0 gui_actual_phase_shift_range17 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg0 Actual Phase Shift 0.0 gui_actual_phase_shift_deg1 Actual Phase Shift 0.0 gui_actual_phase_shift_deg2 Actual Phase Shift 0.0 gui_actual_phase_shift_deg3 Actual Phase Shift 0.0 gui_actual_phase_shift_deg4 Actual Phase Shift 0.0 gui_actual_phase_shift_deg5 Actual Phase Shift 0.0 gui_actual_phase_shift_deg6 Actual Phase Shift 0.0 gui_actual_phase_shift_deg7 Actual Phase Shift 0.0 gui_actual_phase_shift_deg8 Actual Phase Shift 0.0 gui_actual_phase_shift_deg9 Actual Phase Shift 0.0 gui_actual_phase_shift_deg10 Actual Phase Shift 0.0 gui_actual_phase_shift_deg11 Actual Phase Shift 0.0 gui_actual_phase_shift_deg12 Actual Phase Shift 0.0 gui_actual_phase_shift_deg13 Actual Phase Shift 0.0 gui_actual_phase_shift_deg14 Actual Phase Shift 0.0 gui_actual_phase_shift_deg15 Actual Phase Shift 0.0 gui_actual_phase_shift_deg16 Actual Phase Shift 0.0 gui_actual_phase_shift_deg17 Actual Phase Shift 0.0 gui_actual_phase_shift_deg_range0 Legal Phase Shifts 0.0,1.0,1.1,1.1,1.1,1.2 gui_actual_phase_shift_deg_range1 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range2 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range3 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range4 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range5 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range6 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range7 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range8 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range9 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range10 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range11 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range12 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range13 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range14 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range15 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range16 Legal Phase Shifts 0.0 gui_actual_phase_shift_deg_range17 Legal Phase Shifts 0.0 gui_duty_cycle0 Desired Duty Cycle 50.0 gui_duty_cycle1 Desired Duty Cycle 50.0 gui_duty_cycle2 Desired Duty Cycle 50.0 gui_duty_cycle3 Desired Duty Cycle 50.0 gui_duty_cycle4 Desired Duty Cycle 50.0 gui_duty_cycle5 Desired Duty Cycle 50.0 gui_duty_cycle6 Desired Duty Cycle 50.0 gui_duty_cycle7 Desired Duty Cycle 50.0 gui_duty_cycle8 Desired Duty Cycle 50.0 gui_duty_cycle9 Desired Duty Cycle 50.0 gui_duty_cycle10 Desired Duty Cycle 50.0 gui_duty_cycle11 Desired Duty Cycle 50.0 gui_duty_cycle12 Desired Duty Cycle 50.0 gui_duty_cycle13 Desired Duty Cycle 50.0 gui_duty_cycle14 Desired Duty Cycle 50.0 gui_duty_cycle15 Desired Duty Cycle 50.0 gui_duty_cycle16 Desired Duty Cycle 50.0 gui_duty_cycle17 Desired Duty Cycle 50.0 gui_actual_duty_cycle0 Actual duty cycle 50.0 gui_actual_duty_cycle1 Actual duty cycle 50.0 gui_actual_duty_cycle2 Actual duty cycle 50.0 gui_actual_duty_cycle3 Actual duty cycle 50.0 gui_actual_duty_cycle4 Actual duty cycle 50.0 gui_actual_duty_cycle5 Actual duty cycle 50.0 gui_actual_duty_cycle6 Actual duty cycle 50.0 gui_actual_duty_cycle7 Actual duty cycle 50.0 gui_actual_duty_cycle8 Actual duty cycle 50.0 gui_actual_duty_cycle9 Actual duty cycle 50.0 gui_actual_duty_cycle10 Actual duty cycle 50.0 gui_actual_duty_cycle11 Actual duty cycle 50.0 gui_actual_duty_cycle12 Actual duty cycle 50.0 gui_actual_duty_cycle13 Actual duty cycle 50.0 gui_actual_duty_cycle14 Actual duty cycle 50.0 gui_actual_duty_cycle15 Actual duty cycle 50.0 gui_actual_duty_cycle16 Actual duty cycle 50.0 gui_actual_duty_cycle17 Actual duty cycle 50.0 gui_actual_duty_cycle_range0 Legal Duty Cycles 48.57,48.68,48.81,50.0,51.16,51.28 gui_actual_duty_cycle_range1 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range2 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range3 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range4 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range5 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range6 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range7 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range8 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range9 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range10 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range11 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range12 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range13 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range14 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range15 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range16 Legal Duty Cycles 50.0 gui_actual_duty_cycle_range17 Legal Duty Cycles 50.0 parameterTable_names Parameter Names M-Counter Divide Setting,N-Counter Divide Setting,VCO Frequency,C-Counter-0 Divide Setting,C-Counter-1 Divide Setting,C-Counter-2 Divide Setting,C-Counter-3 Divide Setting,C-Counter-4 Divide Setting,C-Counter-5 Divide Setting,C-Counter-6 Divide Setting,C-Counter-7 Divide Setting,C-Counter-8 Divide Setting,PLL Auto Reset,M-Counter Hi Divide,M-Counter Lo Divide,M-Counter Even Duty Enable,M-Counter Bypass Enable,N-Counter Hi Divide,N-Counter Lo Divide,N-Counter Even Duty Enable,N-Counter Bypass Enable,C-Counter-0 Hi Divide,C-Counter-1 Hi Divide,C-Counter-2 Hi Divide,C-Counter-3 Hi Divide,C-Counter-4 Hi Divide,C-Counter-5 Hi Divide,C-Counter-6 Hi Divide,C-Counter-7 Hi Divide,C-Counter-8 Hi Divide,C-Counter-0 Lo Divide,C-Counter-1 Lo Divide,C-Counter-2 Lo Divide,C-Counter-3 Lo Divide,C-Counter-4 Lo Divide,C-Counter-5 Lo Divide,C-Counter-6 Lo Divide,C-Counter-7 Lo Divide,C-Counter-8 Lo Divide,C-Counter-0 Even Duty Enable,C-Counter-1 Even Duty Enable,C-Counter-2 Even Duty Enable,C-Counter-3 Even Duty Enable,C-Counter-4 Even Duty Enable,C-Counter-5 Even Duty Enable,C-Counter-6 Even Duty Enable,C-Counter-7 Even Duty Enable,C-Counter-8 Even Duty Enable,C-Counter-0 Bypass Enable,C-Counter-1 Bypass Enable,C-Counter-2 Bypass Enable,C-Counter-3 Bypass Enable,C-Counter-4 Bypass Enable,C-Counter-5 Bypass Enable,C-Counter-6 Bypass Enable,C-Counter-7 Bypass Enable,C-Counter-8 Bypass Enable,C-Counter-0 Preset,C-Counter-1 Preset,C-Counter-2 Preset,C-Counter-3 Preset,C-Counter-4 Preset,C-Counter-5 Preset,C-Counter-6 Preset,C-Counter-7 Preset,C-Counter-8 Preset,C-Counter-0 Phase Mux Preset,C-Counter-1 Phase Mux Preset,C-Counter-2 Phase Mux Preset,C-Counter-3 Phase Mux Preset,C-Counter-4 Phase Mux Preset,C-Counter-5 Phase Mux Preset,C-Counter-6 Phase Mux Preset,C-Counter-7 Phase Mux Preset,C-Counter-8 Phase Mux Preset,Charge Pump Current,Bandwidth Control parameterTable_values Parameter Values 6,1,600.0 MHz,18,1,1,1,1,1,1,1,1,false,3,3,false,false,256,256,false,true,9,256,256,256,256,256,256,256,256,9,256,256,256,256,256,256,256,256,false,false,false,false,false,false,false,false,false,false,true,true,true,true,true,true,true,true,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,pll_cp_setting14,pll_bw_res_setting3 mifTable_names MIF File Property The MIF file specified does not yet exist mifTable_values Values pll_m_cnt_basic pll_m_cnt_basic 1 pll_m_cnt pll_m_cnt 1 prot_mode prot_mode BASIC m_cnt_hi_div m_cnt_hi_div 3 eff_m_cnt eff_m_cnt 1 multiply_factor multiply_factor 6 use_core_refclk use_core_refclk false m_cnt_lo_div m_cnt_lo_div 3 n_cnt_hi_div n_cnt_hi_div 256 n_cnt_lo_div n_cnt_lo_div 256 m_cnt_bypass_en m_cnt_bypass_en false n_cnt_bypass_en n_cnt_bypass_en true m_cnt_odd_div_duty_en m_cnt_odd_div_duty_en false n_cnt_odd_div_duty_en n_cnt_odd_div_duty_en false pll_vco_div pll_vco_div 1 pll_cp_current pll_cp_current pll_cp_setting14 pll_bwctrl pll_bwctrl pll_bw_res_setting3 pll_ripplecap_ctrl pll_ripplecap_ctrl pll_fractional_division pll_fractional_division 1 fractional_vco_multiplier fractional_vco_multiplier false reference_clock_frequency reference_clock_frequency 100.0 MHz pll_fractional_cout pll_fractional_cout 1 pll_dsm_out_sel pll_dsm_out_sel 1st_order operation_mode operation_mode direct number_of_clocks number_of_clocks 1 number_of_outclks number_of_outclks 1 pll_vcoph_div pll_vcoph_div 1 pll_type pll_type Cyclone 10 GX pll_subtype pll_subtype General pll_output_clk_frequency pll_output_clk_frequency 600.0 MHz pll_pfd_frequency pll_pfd_frequency 100.0 MHz mimic_fbclk_type mimic_fbclk_type gclk pll_bw_sel pll_bw_sel Low pll_slf_rst pll_slf_rst false pll_fbclk_mux_1 pll_fbclk_mux_1 pll_fbclk_mux_1_glb pll_fbclk_mux_2 pll_fbclk_mux_2 pll_fbclk_mux_2_m_cnt pll_m_cnt_in_src pll_m_cnt_in_src c_m_cnt_in_src_ph_mux_clk pll_clkin_0_src pll_clkin_0_src clk_0 refclk1_frequency refclk1_frequency 100.0 MHz pll_clk_loss_sw_en pll_clk_loss_sw_en false pll_manu_clk_sw_en pll_manu_clk_sw_en false pll_auto_clk_sw_en pll_auto_clk_sw_en false pll_clkin_1_src pll_clkin_1_src clk_0 pll_clk_sw_dly pll_clk_sw_dly 0 pll_extclk_0_cnt_src pll_extclk_0_cnt_src pll_extclk_cnt_src_vss pll_extclk_1_cnt_src pll_extclk_1_cnt_src pll_extclk_cnt_src_vss pll_lock_fltr_cfg pll_lock_fltr_cfg 100 pll_unlock_fltr_cfg pll_unlock_fltr_cfg 2 lock_mode lock_mode low_lock_time clock_to_compensate clock_to_compensate 0 clock_name_global clock_name_global false pll_freqcal_en pll_freqcal_en true pll_defer_cal_user_mode pll_defer_cal_user_mode true dprio_interface_sel dprio_interface_sel 3 merging_permitted merging_permitted false c_cnt_hi_div0 c_cnt_hi_div0 9 c_cnt_hi_div1 c_cnt_hi_div1 256 c_cnt_hi_div2 c_cnt_hi_div2 256 c_cnt_hi_div3 c_cnt_hi_div3 256 c_cnt_hi_div4 c_cnt_hi_div4 256 c_cnt_hi_div5 c_cnt_hi_div5 256 c_cnt_hi_div6 c_cnt_hi_div6 256 c_cnt_hi_div7 c_cnt_hi_div7 256 c_cnt_hi_div8 c_cnt_hi_div8 256 c_cnt_hi_div9 c_cnt_hi_div9 1 c_cnt_hi_div10 c_cnt_hi_div10 1 c_cnt_hi_div11 c_cnt_hi_div11 1 c_cnt_hi_div12 c_cnt_hi_div12 1 c_cnt_hi_div13 c_cnt_hi_div13 1 c_cnt_hi_div14 c_cnt_hi_div14 1 c_cnt_hi_div15 c_cnt_hi_div15 1 c_cnt_hi_div16 c_cnt_hi_div16 1 c_cnt_hi_div17 c_cnt_hi_div17 1 c_cnt_lo_div0 c_cnt_lo_div0 9 c_cnt_lo_div1 c_cnt_lo_div1 256 c_cnt_lo_div2 c_cnt_lo_div2 256 c_cnt_lo_div3 c_cnt_lo_div3 256 c_cnt_lo_div4 c_cnt_lo_div4 256 c_cnt_lo_div5 c_cnt_lo_div5 256 c_cnt_lo_div6 c_cnt_lo_div6 256 c_cnt_lo_div7 c_cnt_lo_div7 256 c_cnt_lo_div8 c_cnt_lo_div8 256 c_cnt_lo_div9 c_cnt_lo_div9 1 c_cnt_lo_div10 c_cnt_lo_div10 1 c_cnt_lo_div11 c_cnt_lo_div11 1 c_cnt_lo_div12 c_cnt_lo_div12 1 c_cnt_lo_div13 c_cnt_lo_div13 1 c_cnt_lo_div14 c_cnt_lo_div14 1 c_cnt_lo_div15 c_cnt_lo_div15 1 c_cnt_lo_div16 c_cnt_lo_div16 1 c_cnt_lo_div17 c_cnt_lo_div17 1 c_cnt_prst0 c_cnt_prst0 1 c_cnt_prst1 c_cnt_prst1 1 c_cnt_prst2 c_cnt_prst2 1 c_cnt_prst3 c_cnt_prst3 1 c_cnt_prst4 c_cnt_prst4 1 c_cnt_prst5 c_cnt_prst5 1 c_cnt_prst6 c_cnt_prst6 1 c_cnt_prst7 c_cnt_prst7 1 c_cnt_prst8 c_cnt_prst8 1 c_cnt_prst9 c_cnt_prst9 1 c_cnt_prst10 c_cnt_prst10 1 c_cnt_prst11 c_cnt_prst11 1 c_cnt_prst12 c_cnt_prst12 1 c_cnt_prst13 c_cnt_prst13 1 c_cnt_prst14 c_cnt_prst14 1 c_cnt_prst15 c_cnt_prst15 1 c_cnt_prst16 c_cnt_prst16 1 c_cnt_prst17 c_cnt_prst17 1 c_cnt_ph_mux_prst0 c_cnt_ph_mux_prst0 0 c_cnt_ph_mux_prst1 c_cnt_ph_mux_prst1 0 c_cnt_ph_mux_prst2 c_cnt_ph_mux_prst2 0 c_cnt_ph_mux_prst3 c_cnt_ph_mux_prst3 0 c_cnt_ph_mux_prst4 c_cnt_ph_mux_prst4 0 c_cnt_ph_mux_prst5 c_cnt_ph_mux_prst5 0 c_cnt_ph_mux_prst6 c_cnt_ph_mux_prst6 0 c_cnt_ph_mux_prst7 c_cnt_ph_mux_prst7 0 c_cnt_ph_mux_prst8 c_cnt_ph_mux_prst8 0 c_cnt_ph_mux_prst9 c_cnt_ph_mux_prst9 0 c_cnt_ph_mux_prst10 c_cnt_ph_mux_prst10 0 c_cnt_ph_mux_prst11 c_cnt_ph_mux_prst11 0 c_cnt_ph_mux_prst12 c_cnt_ph_mux_prst12 0 c_cnt_ph_mux_prst13 c_cnt_ph_mux_prst13 0 c_cnt_ph_mux_prst14 c_cnt_ph_mux_prst14 0 c_cnt_ph_mux_prst15 c_cnt_ph_mux_prst15 0 c_cnt_ph_mux_prst16 c_cnt_ph_mux_prst16 0 c_cnt_ph_mux_prst17 c_cnt_ph_mux_prst17 0 c_cnt_in_src0 c_cnt_in_src0 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src1 c_cnt_in_src1 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src2 c_cnt_in_src2 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src3 c_cnt_in_src3 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src4 c_cnt_in_src4 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src5 c_cnt_in_src5 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src6 c_cnt_in_src6 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src7 c_cnt_in_src7 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src8 c_cnt_in_src8 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src9 c_cnt_in_src9 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src10 c_cnt_in_src10 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src11 c_cnt_in_src11 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src12 c_cnt_in_src12 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src13 c_cnt_in_src13 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src14 c_cnt_in_src14 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src15 c_cnt_in_src15 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src16 c_cnt_in_src16 c_m_cnt_in_src_ph_mux_clk c_cnt_in_src17 c_cnt_in_src17 c_m_cnt_in_src_ph_mux_clk c_cnt_bypass_en0 c_cnt_bypass_en0 false c_cnt_bypass_en1 c_cnt_bypass_en1 true c_cnt_bypass_en2 c_cnt_bypass_en2 true c_cnt_bypass_en3 c_cnt_bypass_en3 true c_cnt_bypass_en4 c_cnt_bypass_en4 true c_cnt_bypass_en5 c_cnt_bypass_en5 true c_cnt_bypass_en6 c_cnt_bypass_en6 true c_cnt_bypass_en7 c_cnt_bypass_en7 true c_cnt_bypass_en8 c_cnt_bypass_en8 true c_cnt_bypass_en9 c_cnt_bypass_en9 true c_cnt_bypass_en10 c_cnt_bypass_en10 true c_cnt_bypass_en11 c_cnt_bypass_en11 true c_cnt_bypass_en12 c_cnt_bypass_en12 true c_cnt_bypass_en13 c_cnt_bypass_en13 true c_cnt_bypass_en14 c_cnt_bypass_en14 true c_cnt_bypass_en15 c_cnt_bypass_en15 true c_cnt_bypass_en16 c_cnt_bypass_en16 true c_cnt_bypass_en17 c_cnt_bypass_en17 true c_cnt_odd_div_duty_en0 c_cnt_odd_div_duty_en0 false c_cnt_odd_div_duty_en1 c_cnt_odd_div_duty_en1 false c_cnt_odd_div_duty_en2 c_cnt_odd_div_duty_en2 false c_cnt_odd_div_duty_en3 c_cnt_odd_div_duty_en3 false c_cnt_odd_div_duty_en4 c_cnt_odd_div_duty_en4 false c_cnt_odd_div_duty_en5 c_cnt_odd_div_duty_en5 false c_cnt_odd_div_duty_en6 c_cnt_odd_div_duty_en6 false c_cnt_odd_div_duty_en7 c_cnt_odd_div_duty_en7 false c_cnt_odd_div_duty_en8 c_cnt_odd_div_duty_en8 false c_cnt_odd_div_duty_en9 c_cnt_odd_div_duty_en9 false c_cnt_odd_div_duty_en10 c_cnt_odd_div_duty_en10 false c_cnt_odd_div_duty_en11 c_cnt_odd_div_duty_en11 false c_cnt_odd_div_duty_en12 c_cnt_odd_div_duty_en12 false c_cnt_odd_div_duty_en13 c_cnt_odd_div_duty_en13 false c_cnt_odd_div_duty_en14 c_cnt_odd_div_duty_en14 false c_cnt_odd_div_duty_en15 c_cnt_odd_div_duty_en15 false c_cnt_odd_div_duty_en16 c_cnt_odd_div_duty_en16 false c_cnt_odd_div_duty_en17 c_cnt_odd_div_duty_en17 false output_clock_frequency0 output_clock_frequency0 33.333333 MHz output_clock_frequency1 output_clock_frequency1 0 ps output_clock_frequency2 output_clock_frequency2 0 ps output_clock_frequency3 output_clock_frequency3 0 ps output_clock_frequency4 output_clock_frequency4 0 ps output_clock_frequency5 output_clock_frequency5 0 ps output_clock_frequency6 output_clock_frequency6 0 ps output_clock_frequency7 output_clock_frequency7 0 ps output_clock_frequency8 output_clock_frequency8 0 ps output_clock_frequency9 output_clock_frequency9 0 MHz output_clock_frequency10 output_clock_frequency10 0 MHz output_clock_frequency11 output_clock_frequency11 0 MHz output_clock_frequency12 output_clock_frequency12 0 MHz output_clock_frequency13 output_clock_frequency13 0 MHz output_clock_frequency14 output_clock_frequency14 0 MHz output_clock_frequency15 output_clock_frequency15 0 MHz output_clock_frequency16 output_clock_frequency16 0 MHz output_clock_frequency17 output_clock_frequency17 0 MHz phase_shift0 phase_shift0 0 ps phase_shift1 phase_shift1 0 ps phase_shift2 phase_shift2 0 ps phase_shift3 phase_shift3 0 ps phase_shift4 phase_shift4 0 ps phase_shift5 phase_shift5 0 ps phase_shift6 phase_shift6 0 ps phase_shift7 phase_shift7 0 ps phase_shift8 phase_shift8 0 ps phase_shift9 phase_shift9 0 ps phase_shift10 phase_shift10 0 ps phase_shift11 phase_shift11 0 ps phase_shift12 phase_shift12 0 ps phase_shift13 phase_shift13 0 ps phase_shift14 phase_shift14 0 ps phase_shift15 phase_shift15 0 ps phase_shift16 phase_shift16 0 ps phase_shift17 phase_shift17 0 ps duty_cycle0 duty_cycle0 50 duty_cycle1 duty_cycle1 50 duty_cycle2 duty_cycle2 50 duty_cycle3 duty_cycle3 50 duty_cycle4 duty_cycle4 50 duty_cycle5 duty_cycle5 50 duty_cycle6 duty_cycle6 50 duty_cycle7 duty_cycle7 50 duty_cycle8 duty_cycle8 50 duty_cycle9 duty_cycle9 50 duty_cycle10 duty_cycle10 50 duty_cycle11 duty_cycle11 50 duty_cycle12 duty_cycle12 50 duty_cycle13 duty_cycle13 50 duty_cycle14 duty_cycle14 50 duty_cycle15 duty_cycle15 50 duty_cycle16 duty_cycle16 50 duty_cycle17 duty_cycle17 50 clock_name_0 clock_name_0 clk33 clock_name_1 clock_name_1 clock_name_2 clock_name_2 clock_name_3 clock_name_3 clock_name_4 clock_name_4 clock_name_5 clock_name_5 clock_name_6 clock_name_6 clock_name_7 clock_name_7 clock_name_8 clock_name_8 clock_name_global_0 clock_name_global_0 false clock_name_global_1 clock_name_global_1 false clock_name_global_2 clock_name_global_2 false clock_name_global_3 clock_name_global_3 false clock_name_global_4 clock_name_global_4 false clock_name_global_5 clock_name_global_5 false clock_name_global_6 clock_name_global_6 false clock_name_global_7 clock_name_global_7 false clock_name_global_8 clock_name_global_8 false divide_factor0 divide_factor0 1 divide_factor1 divide_factor1 1 divide_factor2 divide_factor2 1 divide_factor3 divide_factor3 1 divide_factor4 divide_factor4 1 divide_factor5 divide_factor5 1 divide_factor6 divide_factor6 1 divide_factor7 divide_factor7 1 divide_factor8 divide_factor8 1 pll_tclk_mux_en pll_tclk_mux_en false pll_tclk_sel pll_tclk_sel pll_tclk_m_src pll_vco_freq_band_0 pll_vco_freq_band_0 pll_freq_clk0_disabled pll_vco_freq_band_1 pll_vco_freq_band_1 pll_freq_clk1_disabled pll_freqcal_req_flag pll_freqcal_req_flag true cal_converge cal_converge false cal_error cal_error cal_clean pll_cal_done pll_cal_done false include_iossm include_iossm false cal_code_hex_file cal_code_hex_file iossm.hex parameter_table_hex_file parameter_table_hex_file seq_params_sim.hex iossm_nios_sim_clk_period_ps iossm_nios_sim_clk_period_ps 1333 hp_number_of_family_allowable_clocks hp_number_of_family_allowable_clocks 9 hp_previous_num_clocks hp_previous_num_clocks 1 hp_actual_vco_frequency_fp hp_actual_vco_frequency_fp 600.0 hp_parameter_update_message hp_parameter_update_message hp_qsys_scripting_mode hp_qsys_scripting_mode false hp_actual_output_clock_frequency_fp0 hp_actual_output_clock_frequency_fp0 33.33333333333333 hp_actual_output_clock_frequency_fp1 hp_actual_output_clock_frequency_fp1 100.0 hp_actual_output_clock_frequency_fp2 hp_actual_output_clock_frequency_fp2 100.0 hp_actual_output_clock_frequency_fp3 hp_actual_output_clock_frequency_fp3 100.0 hp_actual_output_clock_frequency_fp4 hp_actual_output_clock_frequency_fp4 100.0 hp_actual_output_clock_frequency_fp5 hp_actual_output_clock_frequency_fp5 100.0 hp_actual_output_clock_frequency_fp6 hp_actual_output_clock_frequency_fp6 100.0 hp_actual_output_clock_frequency_fp7 hp_actual_output_clock_frequency_fp7 100.0 hp_actual_output_clock_frequency_fp8 hp_actual_output_clock_frequency_fp8 100.0 hp_actual_output_clock_frequency_fp9 hp_actual_output_clock_frequency_fp9 100.0 hp_actual_output_clock_frequency_fp10 hp_actual_output_clock_frequency_fp10 100.0 hp_actual_output_clock_frequency_fp11 hp_actual_output_clock_frequency_fp11 100.0 hp_actual_output_clock_frequency_fp12 hp_actual_output_clock_frequency_fp12 100.0 hp_actual_output_clock_frequency_fp13 hp_actual_output_clock_frequency_fp13 100.0 hp_actual_output_clock_frequency_fp14 hp_actual_output_clock_frequency_fp14 100.0 hp_actual_output_clock_frequency_fp15 hp_actual_output_clock_frequency_fp15 100.0 hp_actual_output_clock_frequency_fp16 hp_actual_output_clock_frequency_fp16 100.0 hp_actual_output_clock_frequency_fp17 hp_actual_output_clock_frequency_fp17 100.0 hp_actual_phase_shift_fp0 hp_actual_phase_shift_fp0 0.0 hp_actual_phase_shift_fp1 hp_actual_phase_shift_fp1 0.0 hp_actual_phase_shift_fp2 hp_actual_phase_shift_fp2 0.0 hp_actual_phase_shift_fp3 hp_actual_phase_shift_fp3 0.0 hp_actual_phase_shift_fp4 hp_actual_phase_shift_fp4 0.0 hp_actual_phase_shift_fp5 hp_actual_phase_shift_fp5 0.0 hp_actual_phase_shift_fp6 hp_actual_phase_shift_fp6 0.0 hp_actual_phase_shift_fp7 hp_actual_phase_shift_fp7 0.0 hp_actual_phase_shift_fp8 hp_actual_phase_shift_fp8 0.0 hp_actual_phase_shift_fp9 hp_actual_phase_shift_fp9 0.0 hp_actual_phase_shift_fp10 hp_actual_phase_shift_fp10 0.0 hp_actual_phase_shift_fp11 hp_actual_phase_shift_fp11 0.0 hp_actual_phase_shift_fp12 hp_actual_phase_shift_fp12 0.0 hp_actual_phase_shift_fp13 hp_actual_phase_shift_fp13 0.0 hp_actual_phase_shift_fp14 hp_actual_phase_shift_fp14 0.0 hp_actual_phase_shift_fp15 hp_actual_phase_shift_fp15 0.0 hp_actual_phase_shift_fp16 hp_actual_phase_shift_fp16 0.0 hp_actual_phase_shift_fp17 hp_actual_phase_shift_fp17 0.0 hp_actual_duty_cycle_fp0 hp_actual_duty_cycle_fp0 50.0 hp_actual_duty_cycle_fp1 hp_actual_duty_cycle_fp1 50.0 hp_actual_duty_cycle_fp2 hp_actual_duty_cycle_fp2 50.0 hp_actual_duty_cycle_fp3 hp_actual_duty_cycle_fp3 50.0 hp_actual_duty_cycle_fp4 hp_actual_duty_cycle_fp4 50.0 hp_actual_duty_cycle_fp5 hp_actual_duty_cycle_fp5 50.0 hp_actual_duty_cycle_fp6 hp_actual_duty_cycle_fp6 50.0 hp_actual_duty_cycle_fp7 hp_actual_duty_cycle_fp7 50.0 hp_actual_duty_cycle_fp8 hp_actual_duty_cycle_fp8 50.0 hp_actual_duty_cycle_fp9 hp_actual_duty_cycle_fp9 50.0 hp_actual_duty_cycle_fp10 hp_actual_duty_cycle_fp10 50.0 hp_actual_duty_cycle_fp11 hp_actual_duty_cycle_fp11 50.0 hp_actual_duty_cycle_fp12 hp_actual_duty_cycle_fp12 50.0 hp_actual_duty_cycle_fp13 hp_actual_duty_cycle_fp13 50.0 hp_actual_duty_cycle_fp14 hp_actual_duty_cycle_fp14 50.0 hp_actual_duty_cycle_fp15 hp_actual_duty_cycle_fp15 50.0 hp_actual_duty_cycle_fp16 hp_actual_duty_cycle_fp16 50.0 hp_actual_duty_cycle_fp17 hp_actual_duty_cycle_fp17 50.0 embeddedsw.dts.compatible altr,pll embeddedsw.dts.group clock embeddedsw.dts.vendor altr device Device 10CX220YF780E5G deviceFamily Device family Cyclone 10 GX deviceSpeedGrade Device Speed Grade 5 generationId Generation Id 0 bonusData bonusData bonusData { element iopll_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos> <entry> <key>outclk0</key> <value> <connectionPointName>outclk0</connectionPointName> <suppliedSystemInfos/> <consumedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>33333333</value> </entry> </consumedSystemInfos> </value> </entry> </connPtSystemInfos> </systemInfosDefinition> false false