Intel Corporation c10pcie_gen2x4 pcie_a10_hip_0 19.1 pld_clk clk pld_clk clockRate Clock rate 250000000 externallyDriven Externally driven false ptfSchematicName PTF schematic name coreclkout_hip clk coreclkout_hip associatedDirectClock Associated direct clock clockRate Clock rate 250000000 clockRateKnown Clock rate known true externallyDriven Externally driven false ptfSchematicName PTF schematic name refclk clk refclk clockRate Clock rate 100000000 externallyDriven Externally driven false ptfSchematicName PTF schematic name npor npor npor pin_perst pin_perst associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false hip_rst pld_core_ready pld_core_ready pld_clk_inuse pld_clk_inuse serdes_pll_locked serdes_pll_locked reset_status reset_status testin_zero testin_zero associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false hip_ctrl test_in test_in simu_mode_pipe simu_mode_pipe associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false hip_status derr_cor_ext_rcv derr_cor_ext_rcv derr_cor_ext_rpl derr_cor_ext_rpl derr_rpl derr_rpl dlup dlup dlup_exit dlup_exit ev128ns ev128ns ev1us ev1us hotrst_exit hotrst_exit int_status int_status l2_exit l2_exit lane_act lane_act ltssmstate ltssmstate rx_par_err rx_par_err tx_par_err tx_par_err cfg_par_err cfg_par_err ko_cpl_spc_header ko_cpl_spc_header ko_cpl_spc_data ko_cpl_spc_data associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false currentspeed currentspeed currentspeed associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false tx_st startofpacket tx_st_sop endofpacket tx_st_eop error tx_st_err valid tx_st_valid ready tx_st_ready data tx_st_data associatedClock associatedClock pld_clk associatedReset associatedReset clr_st beatsPerCycle Beats Per Cycle 1 dataBitsPerSymbol Data bits per symbol 64 emptyWithinPacket emptyWithinPacket false errorDescriptor Error descriptor firstSymbolInHighOrderBits First Symbol In High-Order Bits true highOrderSymbolAtMSB highOrderSymbolAtMSB false maxChannel Maximum channel 0 packetDescription Packet description prSafe Partial Reconfiguration Safe false readyAllowance Ready allowance 0 readyLatency Ready latency 3 symbolsPerBeat Symbols per beat 1 rx_st startofpacket rx_st_sop endofpacket rx_st_eop error rx_st_err valid rx_st_valid ready rx_st_ready data rx_st_data associatedClock associatedClock pld_clk associatedReset associatedReset clr_st beatsPerCycle Beats Per Cycle 1 dataBitsPerSymbol Data bits per symbol 64 emptyWithinPacket emptyWithinPacket false errorDescriptor Error descriptor firstSymbolInHighOrderBits First Symbol In High-Order Bits true highOrderSymbolAtMSB highOrderSymbolAtMSB false maxChannel Maximum channel 0 packetDescription Packet description prSafe Partial Reconfiguration Safe false readyAllowance Ready allowance 0 readyLatency Ready latency 3 symbolsPerBeat Symbols per beat 1 clr_st reset clr_st associatedClock Associated clock coreclkout_hip associatedDirectReset Associated direct reset associatedResetSinks Associated reset sinks none synchronousEdges Synchronous edges BOTH rx_bar rx_st_bar rx_st_bar rx_st_mask rx_st_mask associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false tx_cred tx_cred_data_fc tx_cred_data_fc tx_cred_fc_hip_cons tx_cred_fc_hip_cons tx_cred_fc_infinite tx_cred_fc_infinite tx_cred_hdr_fc tx_cred_hdr_fc tx_cred_fc_sel tx_cred_fc_sel associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false hip_pipe sim_pipe_pclk_in sim_pipe_pclk_in sim_pipe_rate sim_pipe_rate sim_ltssmstate sim_ltssmstate eidleinfersel0 eidleinfersel0 eidleinfersel1 eidleinfersel1 eidleinfersel2 eidleinfersel2 eidleinfersel3 eidleinfersel3 powerdown0 powerdown0 powerdown1 powerdown1 powerdown2 powerdown2 powerdown3 powerdown3 rxpolarity0 rxpolarity0 rxpolarity1 rxpolarity1 rxpolarity2 rxpolarity2 rxpolarity3 rxpolarity3 txcompl0 txcompl0 txcompl1 txcompl1 txcompl2 txcompl2 txcompl3 txcompl3 txdata0 txdata0 txdata1 txdata1 txdata2 txdata2 txdata3 txdata3 txdatak0 txdatak0 txdatak1 txdatak1 txdatak2 txdatak2 txdatak3 txdatak3 txdetectrx0 txdetectrx0 txdetectrx1 txdetectrx1 txdetectrx2 txdetectrx2 txdetectrx3 txdetectrx3 txelecidle0 txelecidle0 txelecidle1 txelecidle1 txelecidle2 txelecidle2 txelecidle3 txelecidle3 txdeemph0 txdeemph0 txdeemph1 txdeemph1 txdeemph2 txdeemph2 txdeemph3 txdeemph3 txmargin0 txmargin0 txmargin1 txmargin1 txmargin2 txmargin2 txmargin3 txmargin3 txswing0 txswing0 txswing1 txswing1 txswing2 txswing2 txswing3 txswing3 phystatus0 phystatus0 phystatus1 phystatus1 phystatus2 phystatus2 phystatus3 phystatus3 rxdata0 rxdata0 rxdata1 rxdata1 rxdata2 rxdata2 rxdata3 rxdata3 rxdatak0 rxdatak0 rxdatak1 rxdatak1 rxdatak2 rxdatak2 rxdatak3 rxdatak3 rxelecidle0 rxelecidle0 rxelecidle1 rxelecidle1 rxelecidle2 rxelecidle2 rxelecidle3 rxelecidle3 rxstatus0 rxstatus0 rxstatus1 rxstatus1 rxstatus2 rxstatus2 rxstatus3 rxstatus3 rxvalid0 rxvalid0 rxvalid1 rxvalid1 rxvalid2 rxvalid2 rxvalid3 rxvalid3 rxdataskip0 rxdataskip0 rxdataskip1 rxdataskip1 rxdataskip2 rxdataskip2 rxdataskip3 rxdataskip3 rxblkst0 rxblkst0 rxblkst1 rxblkst1 rxblkst2 rxblkst2 rxblkst3 rxblkst3 rxsynchd0 rxsynchd0 rxsynchd1 rxsynchd1 rxsynchd2 rxsynchd2 rxsynchd3 rxsynchd3 currentcoeff0 currentcoeff0 currentcoeff1 currentcoeff1 currentcoeff2 currentcoeff2 currentcoeff3 currentcoeff3 currentrxpreset0 currentrxpreset0 currentrxpreset1 currentrxpreset1 currentrxpreset2 currentrxpreset2 currentrxpreset3 currentrxpreset3 txsynchd0 txsynchd0 txsynchd1 txsynchd1 txsynchd2 txsynchd2 txsynchd3 txsynchd3 txblkst0 txblkst0 txblkst1 txblkst1 txblkst2 txblkst2 txblkst3 txblkst3 txdataskip0 txdataskip0 txdataskip1 txdataskip1 txdataskip2 txdataskip2 txdataskip3 txdataskip3 rate0 rate0 rate1 rate1 rate2 rate2 rate3 rate3 associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false hip_serial rx_in0 rx_in0 rx_in1 rx_in1 rx_in2 rx_in2 rx_in3 rx_in3 tx_out0 tx_out0 tx_out1 tx_out1 tx_out2 tx_out2 tx_out3 tx_out3 associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false int_msi app_int_sts app_int_sts app_int_ack app_int_ack app_msi_num app_msi_num app_msi_req app_msi_req app_msi_tc app_msi_tc app_msi_ack app_msi_ack associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false power_mgnt pm_auxpwr pm_auxpwr pm_data pm_data pme_to_cr pme_to_cr pm_event pm_event pme_to_sr pme_to_sr associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false config_tl hpg_ctrler hpg_ctrler tl_cfg_add tl_cfg_add tl_cfg_ctl tl_cfg_ctl tl_cfg_sts tl_cfg_sts cpl_err cpl_err cpl_pending cpl_pending associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH altera_pcie_a10_hip QUARTUS_SYNTH pld_clk in STD_LOGIC QUARTUS_SYNTH coreclkout_hip out STD_LOGIC QUARTUS_SYNTH refclk in STD_LOGIC QUARTUS_SYNTH npor in STD_LOGIC QUARTUS_SYNTH pin_perst in STD_LOGIC QUARTUS_SYNTH pld_core_ready in STD_LOGIC QUARTUS_SYNTH pld_clk_inuse out STD_LOGIC QUARTUS_SYNTH serdes_pll_locked out STD_LOGIC QUARTUS_SYNTH reset_status out STD_LOGIC QUARTUS_SYNTH testin_zero out STD_LOGIC QUARTUS_SYNTH test_in in 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH simu_mode_pipe in STD_LOGIC QUARTUS_SYNTH derr_cor_ext_rcv out STD_LOGIC QUARTUS_SYNTH derr_cor_ext_rpl out STD_LOGIC QUARTUS_SYNTH derr_rpl out STD_LOGIC QUARTUS_SYNTH dlup out STD_LOGIC QUARTUS_SYNTH dlup_exit out STD_LOGIC QUARTUS_SYNTH ev128ns out STD_LOGIC QUARTUS_SYNTH ev1us out STD_LOGIC QUARTUS_SYNTH hotrst_exit out STD_LOGIC QUARTUS_SYNTH int_status out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH l2_exit out STD_LOGIC QUARTUS_SYNTH lane_act out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH ltssmstate out 0 4 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_par_err out STD_LOGIC QUARTUS_SYNTH tx_par_err out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH cfg_par_err out STD_LOGIC QUARTUS_SYNTH ko_cpl_spc_header out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH ko_cpl_spc_data out 0 11 STD_LOGIC_VECTOR QUARTUS_SYNTH currentspeed out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_st_sop in STD_LOGIC_VECTOR QUARTUS_SYNTH tx_st_eop in STD_LOGIC_VECTOR QUARTUS_SYNTH tx_st_err in STD_LOGIC_VECTOR QUARTUS_SYNTH tx_st_valid in STD_LOGIC_VECTOR QUARTUS_SYNTH tx_st_ready out STD_LOGIC QUARTUS_SYNTH tx_st_data in 0 63 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_st_sop out STD_LOGIC_VECTOR QUARTUS_SYNTH rx_st_eop out STD_LOGIC_VECTOR QUARTUS_SYNTH rx_st_err out STD_LOGIC_VECTOR QUARTUS_SYNTH rx_st_valid out STD_LOGIC_VECTOR QUARTUS_SYNTH rx_st_ready in STD_LOGIC QUARTUS_SYNTH rx_st_data out 0 63 STD_LOGIC_VECTOR QUARTUS_SYNTH clr_st out STD_LOGIC QUARTUS_SYNTH rx_st_bar out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_st_mask in STD_LOGIC QUARTUS_SYNTH tx_cred_data_fc out 0 11 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_cred_fc_hip_cons out 0 5 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_cred_fc_infinite out 0 5 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_cred_hdr_fc out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_cred_fc_sel in 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH sim_pipe_pclk_in in STD_LOGIC QUARTUS_SYNTH sim_pipe_rate out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH sim_ltssmstate out 0 4 STD_LOGIC_VECTOR QUARTUS_SYNTH eidleinfersel0 out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH eidleinfersel1 out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH eidleinfersel2 out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH eidleinfersel3 out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH powerdown0 out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH powerdown1 out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH powerdown2 out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH powerdown3 out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rxpolarity0 out STD_LOGIC QUARTUS_SYNTH rxpolarity1 out STD_LOGIC QUARTUS_SYNTH rxpolarity2 out STD_LOGIC QUARTUS_SYNTH rxpolarity3 out STD_LOGIC QUARTUS_SYNTH txcompl0 out STD_LOGIC QUARTUS_SYNTH txcompl1 out STD_LOGIC QUARTUS_SYNTH txcompl2 out STD_LOGIC QUARTUS_SYNTH txcompl3 out STD_LOGIC QUARTUS_SYNTH txdata0 out 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH txdata1 out 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH txdata2 out 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH txdata3 out 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH txdatak0 out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH txdatak1 out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH txdatak2 out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH txdatak3 out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH txdetectrx0 out STD_LOGIC QUARTUS_SYNTH txdetectrx1 out STD_LOGIC QUARTUS_SYNTH txdetectrx2 out STD_LOGIC QUARTUS_SYNTH txdetectrx3 out STD_LOGIC QUARTUS_SYNTH txelecidle0 out STD_LOGIC QUARTUS_SYNTH txelecidle1 out STD_LOGIC QUARTUS_SYNTH txelecidle2 out STD_LOGIC QUARTUS_SYNTH txelecidle3 out STD_LOGIC QUARTUS_SYNTH txdeemph0 out STD_LOGIC QUARTUS_SYNTH txdeemph1 out STD_LOGIC QUARTUS_SYNTH txdeemph2 out STD_LOGIC QUARTUS_SYNTH txdeemph3 out STD_LOGIC QUARTUS_SYNTH txmargin0 out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH txmargin1 out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH txmargin2 out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH txmargin3 out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH txswing0 out STD_LOGIC QUARTUS_SYNTH txswing1 out STD_LOGIC QUARTUS_SYNTH txswing2 out STD_LOGIC QUARTUS_SYNTH txswing3 out STD_LOGIC QUARTUS_SYNTH phystatus0 in STD_LOGIC QUARTUS_SYNTH phystatus1 in STD_LOGIC QUARTUS_SYNTH phystatus2 in STD_LOGIC QUARTUS_SYNTH phystatus3 in STD_LOGIC QUARTUS_SYNTH rxdata0 in 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH rxdata1 in 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH rxdata2 in 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH rxdata3 in 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH rxdatak0 in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rxdatak1 in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rxdatak2 in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rxdatak3 in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rxelecidle0 in STD_LOGIC QUARTUS_SYNTH rxelecidle1 in STD_LOGIC QUARTUS_SYNTH rxelecidle2 in STD_LOGIC QUARTUS_SYNTH rxelecidle3 in STD_LOGIC QUARTUS_SYNTH rxstatus0 in 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH rxstatus1 in 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH rxstatus2 in 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH rxstatus3 in 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH rxvalid0 in STD_LOGIC QUARTUS_SYNTH rxvalid1 in STD_LOGIC QUARTUS_SYNTH rxvalid2 in STD_LOGIC QUARTUS_SYNTH rxvalid3 in STD_LOGIC QUARTUS_SYNTH rxdataskip0 in STD_LOGIC QUARTUS_SYNTH rxdataskip1 in STD_LOGIC QUARTUS_SYNTH rxdataskip2 in STD_LOGIC QUARTUS_SYNTH rxdataskip3 in STD_LOGIC QUARTUS_SYNTH rxblkst0 in STD_LOGIC QUARTUS_SYNTH rxblkst1 in STD_LOGIC QUARTUS_SYNTH rxblkst2 in STD_LOGIC QUARTUS_SYNTH rxblkst3 in STD_LOGIC QUARTUS_SYNTH rxsynchd0 in 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rxsynchd1 in 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rxsynchd2 in 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rxsynchd3 in 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH currentcoeff0 out 0 17 STD_LOGIC_VECTOR QUARTUS_SYNTH currentcoeff1 out 0 17 STD_LOGIC_VECTOR QUARTUS_SYNTH currentcoeff2 out 0 17 STD_LOGIC_VECTOR QUARTUS_SYNTH currentcoeff3 out 0 17 STD_LOGIC_VECTOR QUARTUS_SYNTH currentrxpreset0 out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH currentrxpreset1 out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH currentrxpreset2 out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH currentrxpreset3 out 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH txsynchd0 out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH txsynchd1 out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH txsynchd2 out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH txsynchd3 out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH txblkst0 out STD_LOGIC QUARTUS_SYNTH txblkst1 out STD_LOGIC QUARTUS_SYNTH txblkst2 out STD_LOGIC QUARTUS_SYNTH txblkst3 out STD_LOGIC QUARTUS_SYNTH txdataskip0 out STD_LOGIC QUARTUS_SYNTH txdataskip1 out STD_LOGIC QUARTUS_SYNTH txdataskip2 out STD_LOGIC QUARTUS_SYNTH txdataskip3 out STD_LOGIC QUARTUS_SYNTH rate0 out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rate1 out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rate2 out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rate3 out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_in0 in STD_LOGIC QUARTUS_SYNTH rx_in1 in STD_LOGIC QUARTUS_SYNTH rx_in2 in STD_LOGIC QUARTUS_SYNTH rx_in3 in STD_LOGIC QUARTUS_SYNTH tx_out0 out STD_LOGIC QUARTUS_SYNTH tx_out1 out STD_LOGIC QUARTUS_SYNTH tx_out2 out STD_LOGIC QUARTUS_SYNTH tx_out3 out STD_LOGIC QUARTUS_SYNTH app_int_sts in STD_LOGIC QUARTUS_SYNTH app_int_ack out STD_LOGIC QUARTUS_SYNTH app_msi_num in 0 4 STD_LOGIC_VECTOR QUARTUS_SYNTH app_msi_req in STD_LOGIC QUARTUS_SYNTH app_msi_tc in 0 2 STD_LOGIC_VECTOR QUARTUS_SYNTH app_msi_ack out STD_LOGIC QUARTUS_SYNTH pm_auxpwr in STD_LOGIC QUARTUS_SYNTH pm_data in 0 9 STD_LOGIC_VECTOR QUARTUS_SYNTH pme_to_cr in STD_LOGIC QUARTUS_SYNTH pm_event in STD_LOGIC QUARTUS_SYNTH pme_to_sr out STD_LOGIC QUARTUS_SYNTH hpg_ctrler in 0 4 STD_LOGIC_VECTOR QUARTUS_SYNTH tl_cfg_add out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tl_cfg_ctl out 0 31 STD_LOGIC_VECTOR QUARTUS_SYNTH tl_cfg_sts out 0 52 STD_LOGIC_VECTOR QUARTUS_SYNTH cpl_err in 0 6 STD_LOGIC_VECTOR QUARTUS_SYNTH cpl_pending in STD_LOGIC QUARTUS_SYNTH Intel Corporation c10pcie_gen2x4 altera_pcie_a10_hip 19.1 interface_type_hwtcl Application interface type Avalon-ST force_tag_checking_on_hwtcl Force Tag Checking ON 0 app_interface_width_hwtcl Application interface width 64-bit wrala_hwtcl Hard IP mode 1 device_family device_family Cyclone 10 GX base_device base_device NIGHTFURY1 part_trait_device part_trait_device 10CX220YF780E5G bar0_address_width_mux_hwtcl bar0_address_width_mux_hwtcl 10 bar1_address_width_mux_hwtcl bar1_address_width_mux_hwtcl 0 bar2_address_width_mux_hwtcl bar2_address_width_mux_hwtcl 8 bar3_address_width_mux_hwtcl bar3_address_width_mux_hwtcl 0 bar4_address_width_mux_hwtcl bar4_address_width_mux_hwtcl 0 bar5_address_width_mux_hwtcl bar5_address_width_mux_hwtcl 0 st_signal_width_integer_hwtcl st_signal_width_integer_hwtcl 1 data_width_integer_hwtcl data_width_integer_hwtcl 64 data_width_integer_rxm_txs_hwtcl data_width_integer_rxm_txs_hwtcl 64 data_width_integer_txs_hwtcl data_width_integer_txs_hwtcl 64 data_byte_width_integer_hwtcl data_byte_width_integer_hwtcl 8 reconfig_address_width_integer_hwtcl reconfig_address_width_integer_hwtcl 12 data_byte_width_integer_rxm_txs_hwtcl data_byte_width_integer_rxm_txs_hwtcl 8 data_byte_width_integer_txs_hwtcl data_byte_width_integer_txs_hwtcl 8 burst_count_integer_hwtcl burst_count_integer_hwtcl 7 empty_integer_hwtcl empty_integer_hwtcl 1 port_type_integer_hwtcl port_type_integer_hwtcl 0 link_width_integer_hwtcl link_width_integer_hwtcl 4 lane_rate_integer_hwtcl lane_rate_integer_hwtcl 2 pld_clk_mhz_integer_hwtcl pld_clk_mhz_integer_hwtcl 2500 bar0_type_integer_hwtcl bar0_type_integer_hwtcl 2 bar1_type_integer_hwtcl bar1_type_integer_hwtcl 0 bar2_type_integer_hwtcl bar2_type_integer_hwtcl 1 bar3_type_integer_hwtcl bar3_type_integer_hwtcl 0 bar4_type_integer_hwtcl bar4_type_integer_hwtcl 0 bar5_type_integer_hwtcl bar5_type_integer_hwtcl 0 include_dma_hwtcl include_dma_hwtcl 0 txs_addr_width_integer_hwtcl txs_addr_width_integer_hwtcl 22 interface_type_integer_hwtcl interface_type_integer_hwtcl 0 dma_width_hwtcl dma_width_hwtcl 128 dma_be_width_hwtcl dma_be_width_hwtcl 16 dma_brst_cnt_w_hwtcl dma_brst_cnt_w_hwtcl 6 set_embedded_debug_enable_hwtcl set_embedded_debug_enable_hwtcl 0 set_capability_reg_enable_hwtcl set_capability_reg_enable_hwtcl 0 set_csr_soft_logic_enable_hwtcl set_csr_soft_logic_enable_hwtcl 0 set_prbs_soft_logic_enable_hwtcl set_prbs_soft_logic_enable_hwtcl 0 rcfg_jtag_enable_hwtcl rcfg_jtag_enable_hwtcl 0 cpl_spc_header_hwtcl cpl_spc_header_hwtcl 112 cpl_spc_data_hwtcl cpl_spc_data_hwtcl 440 avmm_addr_width_hwtcl Avalon-MM address width 64 cb_pcie_mode_hwtcl Enable completer-only Endpoint 0 cb_pcie_rx_lite_hwtcl Enable completer-only Endpoint with 4-byte payload 0 cg_impl_cra_av_slave_port_hwtcl Enable control register access (CRA) Avalon-MM slave port 1 cg_enable_advanced_interrupt_hwtcl Export MSI/MSI-X conduit interfaces 0 cg_enable_a2p_interrupt_hwtcl Enable PCIe interrupt at power-on 0 enable_hip_status_for_avmm_hwtcl Enable Hard IP Status Bus when using the AVMM interface 0 internal_controller_hwtcl Instantiate internal descriptor controller 1 enable_rxm_burst_hwtcl Enable burst capability for RXM BAR2 port 0 extended_tag_support_hwtcl Enable 256 tags 0 user_txs_addr_width_hwtcl Address width of accessible PCIe memory space 22 cg_a2p_addr_map_num_entries_hwtcl Number of address pages 2 cg_a2p_addr_map_pass_thru_bits_hwtcl Size of address pages 12 link_width_hwtcl Number of lanes x4 lane_rate_hwtcl Lane rate Gen2 (5.0 Gbps) port_type_hwtcl Port type Native endpoint pcie_spec_version_hwtcl PCI Express base specification version 3.0 rx_buffer_credit_alloc_hwtcl RX buffer credit allocation for received requests vs completions Balanced rx_buffer_post_credit_alloc_display RX Buffer posted credits Header:n/a Data:n/a rx_buffer_nonpost_credit_alloc_display RX Buffer non-posted credits Header:n/a Data:n/a rx_buffer_credit_alloc_display RX Buffer completion credits Header:112 Data:440 rx_cred_ctl_param_hwtcl RX credit control 0 pll_refclk_freq_hwtcl Reference clock frequency 100 MHz set_pld_clk_x1_625MHz_hwtcl Use 62.5 MHz application clock (Gen1x1 only) 0 enable_avst_reset_hwtcl Enable Avalon-ST Reset output port 1 use_rx_st_be_hwtcl Enable RX Avalon-ST data byte enable port 0 use_ast_parity_hwtcl Enable byte parity ports on Avalon-ST interface 0 multiple_packets_per_cycle_hwtcl Enable multiple packets per cycle for the 256-bit interface 0 cvp_enable_hwtcl Enable Configuration via Protocol (CvP) 0 use_tx_cons_cred_sel_hwtcl Enable credit consumed selection port 0 cseb_config_bypass_gui_hwtcl Enable Configuration Bypass (CfgBP) 0 cseb_config_bypass_hwtcl Enable Configuration Bypass (CfgBP) 0 cseb_autonomous_hwtcl Enable Autonomous mode for Config-Bypass 0 speed_change_hwtcl Enable Speed Change to the expected speed 0 hip_reconfig_hwtcl Enable dynamic reconfiguration of PCIe read-only registers 0 xcvr_reconfig_hwtcl Enable Transceiver dynamic reconfiguration 0 export_fpll_output_to_top_level_hwtcl Export the FPLL PCIe clock output to top level 0 export_phy_input_to_top_level_hwtcl Export the PHY HCLK input to the top level 0 enable_lmi_hwtcl Enable local management interface (LMI) 0 adme_enable_hwtcl Enable Altera Debug Master Endpoint (ADME) 0 enable_devkit_conduit_hwtcl Enable FPGA Development Kit connection 0 enable_skp_det enable_skp_det 0 dis_adapt dis_adapt 0 select_design_example_hwtcl Select design PIO enable_example_design_qii_hwtcl Generate a Quartus Project that includes the example design 1 enable_example_design_sim_hwtcl Simulation 1 enable_g3_bypass_equlz_rp_sim_hwtcl Disable equalization for Root Port example design simulation 0 enable_example_design_synth_hwtcl Synthesis 1 enable_example_design_tb_hwtcl Generate the example design testbench 1 apps_type_hwtcl Set apps_type_hwtcl BFM driver value 0 select_design_example_rtl_lang_hwtcl Generated File Format Verilog targeted_devkit_hwtcl Select board Arria 10 GX FPGA Development Kit bar0_type_hwtcl Type 32-bit non-prefetchable memory bar0_address_width_hwtcl Size 10 bar1_type_hwtcl Type Disabled bar1_address_width_hwtcl Size 0 bar2_type_hwtcl Type 64-bit prefetchable memory bar2_address_width_hwtcl Size 8 bar3_type_hwtcl Type Disabled bar3_address_width_hwtcl Size 0 bar4_type_hwtcl Type Disabled bar4_address_width_hwtcl Size 0 bar5_type_hwtcl Type Disabled bar5_address_width_hwtcl Size 0 expansion_base_address_register_hwtcl Size 0 bar0_address_width_avmm_hwtcl Size 0 bar1_address_width_avmm_hwtcl Size 0 bar2_address_width_avmm_hwtcl Size 0 bar3_address_width_avmm_hwtcl Size 0 bar4_address_width_avmm_hwtcl Size 0 bar5_address_width_avmm_hwtcl Size 0 io_window_addr_width_hwtcl Input/Output 0 prefetchable_mem_window_addr_width_hwtcl Prefetchable memory 0 eco_fb332688_dis_hwtcl eco_fb332688_dis_hwtcl 0 vendor_id_hwtcl Vendor ID 4466 device_id_hwtcl Device ID 1 pf0_vf_device_id_hwtcl VF Device ID 0 revision_id_hwtcl Revision ID 1 class_code_hwtcl Class code 0 pf0_subclass_code_hwtcl Subclass code 0 pf0_pci_prog_intfc_byte_hwtcl Programming IF code 0 subsystem_vendor_id_hwtcl Subsystem Vendor ID 0 subsystem_device_id_hwtcl Subsystem Device ID 0 pf0_vf_subsystem_device_id_hwtcl VF Subsystem Device ID 0 maximum_payload_size_hwtcl Maximum payload size 256 extended_tag_field_hwtcl Number of tags supported 64 completion_timeout_hwtcl Completion timeout range ABCD completion_timeout_disable_hwtcl Disable completion timeout 1 enable_completion_timeout_disable_hwtcl enable_completion_timeout_disable_hwtcl 1 advance_error_reporting_hwtcl Enable Advanced Error Reporting (AER) 0 ecrc_check_capable_hwtcl Enable ECRC checking 0 ecrc_gen_capable_hwtcl Enable ECRC generation 0 use_crc_forwarding_hwtcl Enable ECRC forwarding on the Avalon-ST interface 0 track_rxfc_cplbuf_ovf_hwtcl Track RX completion buffer overflow on the Avalon-ST interface 0 port_link_number_hwtcl Link port number(Root Port only) 1 dll_active_report_support_hwtcl Data link layer active reporting(Root Port only) 0 surprise_down_error_support_hwtcl Surprise down reporting (Root Port only) 0 slot_clock_cfg_hwtcl Slot clock configuration 1 msi_multi_message_capable_hwtcl Number of MSI messages requested 1 vsec_id_hwtcl Vendor Specific Extended Capability (VSEC) ID 4466 vsec_cap_hwtcl Vendor Specific Extended Capability (VSEC) Revision 0 user_id_hwtcl User Device or Board Type ID register from the Vendor Specific Extended Capability 0 enable_function_msix_support_hwtcl Implement MSI-X 0 msix_table_size_hwtcl Table size 0 msix_table_offset_hwtcl Table offset 0 msix_table_bir_hwtcl Table BAR indicator 0 msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 msix_pba_bir_hwtcl PBA BAR Indicator 0 enable_slot_register_hwtcl Use Slot Power registers (Root Port only) 0 slot_power_scale_hwtcl Slot power scale 0 slot_power_limit_hwtcl Slot power limit 0 slot_number_hwtcl Slot number 0 endpoint_l0_latency_hwtcl Endpoint L0s acceptable latency 0 endpoint_l1_latency_hwtcl Endpoint L1 acceptable latency 0 deemphasis_enable_hwtcl Gen 2 TX de-emphasis 0 gen3_coeff_1_hwtcl Requested Equalization Far-End TX Preset 8 bfm_drive_interface_clk_hwtcl bfm_drive_interface_clk_hwtcl 1 bfm_drive_interface_npor_hwtcl bfm_drive_interface_npor_hwtcl 1 bfm_drive_interface_pipe_hwtcl bfm_drive_interface_pipe_hwtcl 1 bfm_drive_interface_control_hwtcl bfm_drive_interface_control_hwtcl 1 serial_sim_hwtcl serial_sim_hwtcl 1 enable_pipe32_phyip_ser_driver_hwtcl enable_pipe32_phyip_ser_driver_hwtcl 0 cseb_extend_pci_hwtcl Use PCI extended space 0 cseb_extend_pcie_hwtcl Use PCI Express extended space 0 reserved_debug_hwtcl reserved_debug_hwtcl 0 include_sriov_hwtcl include_sriov_hwtcl 0 app_msi_req_fn_hwtcl app_msi_req_fn_hwtcl 8 cfg_num_vf_width_hwtcl cfg_num_vf_width_hwtcl 8 flr_completed_vf_width_hwtcl flr_completed_vf_width_hwtcl 4 sriov2_en sriov2_en 1 virtio_visible virtio_visible 0 enable_nobar_slection_hwtcl enable_nobar_slection_hwtcl 0 enable_custom_features_hwtcl enable_custom_features_hwtcl 0 pf0_extra_bar_present_hwtcl Enable Extra BAR in PF0 0 pf0_extra_bar_size_hwtcl Extra BAR Size 12 devhide_support_hwtcl Enable Device Hide Feature 0 device_embedded_ep_support_hwtcl Enable RC Integrated End Point 0 total_pf_count_hwtcl Total Physical Functions (PFs) 1 pf0_vf_count_user_hwtcl Total Virtual Functions of Physical Function0 (PF0 VFs) 0 pf1_vf_count_user_hwtcl Total Virtual Functions of Physical Function1 (PF1 VFs) 0 pf2_vf_count_user_hwtcl Total Virtual Functions of Physical Function2 (PF2 VFs) 0 pf3_vf_count_user_hwtcl Total Virtual Functions of Physical Function3 (PF3 VFs) 0 pf0_vf_count_hwtcl pf0_vf_count_hwtcl 0 pf1_vf_count_hwtcl pf1_vf_count_hwtcl 0 pf2_vf_count_hwtcl pf2_vf_count_hwtcl 0 pf3_vf_count_hwtcl pf3_vf_count_hwtcl 0 total_vf_count_hwtcl total_vf_count_hwtcl 4 total_pf_count_width_hwtcl total_pf_count_width_hwtcl 1 total_vf_count_width_hwtcl total_vf_count_width_hwtcl 1 system_page_sizes_supported_hwtcl Supported page sizes 1363 sr_iov_support_hwtcl Enable SR-IOV support 0 include_virtio_capabilities_hwtcl Enable VIRTIO support 0 enable_alternate_link_list_hwtcl Enable Alternative Link List for VIRTIO Capabilities 0 ari_support_hwtcl Enable Alternative Routing-ID Interpretation (ARI) support 0 flr_capability_user_hwtcl Enable Functional Level Reset (FLR) 0 flr_capability_hwtcl flr_capability_hwtcl 0 pf0_virtio_capability_present_hwtcl Enable VIRTIO Capabilities for PF0 0 pf0_virtio_device_specific_cap_present_hwtcl Enable Device Specific Capability for PF0 0 pf0_virtio_cmn_config_bar_indicator_hwtcl BAR Indicator 0 pf0_virtio_cmn_config_bar_offset_hwtcl Offset within BAR 0 pf0_virtio_cmn_config_structure_length_hwtcl Structure Length in Bytes 0 pf0_virtio_notification_bar_indicator_hwtcl BAR Indicator 0 pf0_virtio_notification_bar_offset_hwtcl Offset within BAR 0 pf0_virtio_notification_structure_length_hwtcl Structure Length in Bytes 0 pf0_virtio_notify_off_multiplier_hwtcl Notify Off Multiplier 0 pf0_virtio_isrstatus_bar_indicator_hwtcl BAR Indicator 0 pf0_virtio_isrstatus_bar_offset_hwtcl Offset within BAR 0 pf0_virtio_isrstatus_structure_length_hwtcl Structure Length in Bytes 0 pf0_virtio_devspecific_bar_indicator_hwtcl BAR Indicator 0 pf0_virtio_devspecific_bar_offset_hwtcl Offset within BAR 0 pf0_virtio_devspecific_structure_length_hwtcl Structure Length in Bytes 0 pf0_virtio_pciconfig_access_bar_indicator_hwtcl BAR Indicator 0 pf0_virtio_pciconfig_access_bar_offset_hwtcl Offset within BAR 0 pf0_virtio_pciconfig_access_structure_length_hwtcl Structure Length in Bytes 0 pf1_virtio_capability_present_hwtcl Enable VIRTIO Capabilities for PF1 0 pf1_virtio_device_specific_cap_present_hwtcl Enable Device Specific Capability for PF1 0 pf1_virtio_cmn_config_bar_indicator_hwtcl BAR Indicator 0 pf1_virtio_cmn_config_bar_offset_hwtcl Offset within BAR 0 pf1_virtio_cmn_config_structure_length_hwtcl Structure Length in Bytes 0 pf1_virtio_notification_bar_indicator_hwtcl BAR Indicator 0 pf1_virtio_notification_bar_offset_hwtcl Offset within BAR 0 pf1_virtio_notification_structure_length_hwtcl Structure Length in Bytes 0 pf1_virtio_notify_off_multiplier_hwtcl Notify Off Multiplier 0 pf1_virtio_isrstatus_bar_indicator_hwtcl BAR Indicator 0 pf1_virtio_isrstatus_bar_offset_hwtcl Offset within BAR 0 pf1_virtio_isrstatus_structure_length_hwtcl Structure Length in Bytes 0 pf1_virtio_devspecific_bar_indicator_hwtcl BAR Indicator 0 pf1_virtio_devspecific_bar_offset_hwtcl Offset within BAR 0 pf1_virtio_devspecific_structure_length_hwtcl Structure Length in Bytes 0 pf1_virtio_pciconfig_access_bar_indicator_hwtcl BAR Indicator 0 pf1_virtio_pciconfig_access_bar_offset_hwtcl Offset within BAR 0 pf1_virtio_pciconfig_access_structure_length_hwtcl Structure Length in Bytes 0 pf2_virtio_capability_present_hwtcl Enable VIRTIO Capabilities for PF2 0 pf2_virtio_device_specific_cap_present_hwtcl Enable Device Specific Capability for PF2 0 pf2_virtio_cmn_config_bar_indicator_hwtcl BAR Indicator 0 pf2_virtio_cmn_config_bar_offset_hwtcl Offset within BAR 0 pf2_virtio_cmn_config_structure_length_hwtcl Structure Length in Bytes 0 pf2_virtio_notification_bar_indicator_hwtcl BAR Indicator 0 pf2_virtio_notification_bar_offset_hwtcl Offset within BAR 0 pf2_virtio_notification_structure_length_hwtcl Structure Length in Bytes 0 pf2_virtio_notify_off_multiplier_hwtcl Notify Off Multiplier 0 pf2_virtio_isrstatus_bar_indicator_hwtcl BAR Indicator 0 pf2_virtio_isrstatus_bar_offset_hwtcl Offset within BAR 0 pf2_virtio_isrstatus_structure_length_hwtcl Structure Length in Bytes 0 pf2_virtio_devspecific_bar_indicator_hwtcl BAR Indicator 0 pf2_virtio_devspecific_bar_offset_hwtcl Offset within BAR 0 pf2_virtio_devspecific_structure_length_hwtcl Structure Length in Bytes 0 pf2_virtio_pciconfig_access_bar_indicator_hwtcl BAR Indicator 0 pf2_virtio_pciconfig_access_bar_offset_hwtcl Offset within BAR 0 pf2_virtio_pciconfig_access_structure_length_hwtcl Structure Length in Bytes 0 pf3_virtio_capability_present_hwtcl Enable VIRTIO Capabilities for PF3 0 pf3_virtio_device_specific_cap_present_hwtcl Enable Device Specific Capability for PF3 0 pf3_virtio_cmn_config_bar_indicator_hwtcl BAR Indicator 0 pf3_virtio_cmn_config_bar_offset_hwtcl Offset within BAR 0 pf3_virtio_cmn_config_structure_length_hwtcl Structure Length in Bytes 0 pf3_virtio_notification_bar_indicator_hwtcl BAR Indicator 0 pf3_virtio_notification_bar_offset_hwtcl Offset within BAR 0 pf3_virtio_notification_structure_length_hwtcl Structure Length in Bytes 0 pf3_virtio_notify_off_multiplier_hwtcl Notify Off Multiplier 0 pf3_virtio_isrstatus_bar_indicator_hwtcl BAR Indicator 0 pf3_virtio_isrstatus_bar_offset_hwtcl Offset within BAR 0 pf3_virtio_isrstatus_structure_length_hwtcl Structure Length in Bytes 0 pf3_virtio_devspecific_bar_indicator_hwtcl BAR Indicator 0 pf3_virtio_devspecific_bar_offset_hwtcl Offset within BAR 0 pf3_virtio_devspecific_structure_length_hwtcl Structure Length in Bytes 0 pf3_virtio_pciconfig_access_bar_indicator_hwtcl BAR Indicator 0 pf3_virtio_pciconfig_access_bar_offset_hwtcl Offset within BAR 0 pf3_virtio_pciconfig_access_structure_length_hwtcl Structure Length in Bytes 0 pf4_virtio_capability_present_hwtcl Enable VIRTIO Capabilities for PF4 0 pf4_virtio_device_specific_cap_present_hwtcl Enable Device Specific Capability for PF4 0 pf4_virtio_cmn_config_bar_indicator_hwtcl BAR Indicator 0 pf4_virtio_cmn_config_bar_offset_hwtcl Offset within BAR 0 pf4_virtio_cmn_config_structure_length_hwtcl Structure Length in Bytes 0 pf4_virtio_notification_bar_indicator_hwtcl BAR Indicator 0 pf4_virtio_notification_bar_offset_hwtcl Offset within BAR 0 pf4_virtio_notification_structure_length_hwtcl Structure Length in Bytes 0 pf4_virtio_notify_off_multiplier_hwtcl Notify Off Multiplier 0 pf4_virtio_isrstatus_bar_indicator_hwtcl BAR Indicator 0 pf4_virtio_isrstatus_bar_offset_hwtcl Offset within BAR 0 pf4_virtio_isrstatus_structure_length_hwtcl Structure Length in Bytes 0 pf4_virtio_devspecific_bar_indicator_hwtcl BAR Indicator 0 pf4_virtio_devspecific_bar_offset_hwtcl Offset within BAR 0 pf4_virtio_devspecific_structure_length_hwtcl Structure Length in Bytes 0 pf4_virtio_pciconfig_access_bar_indicator_hwtcl BAR Indicator 0 pf4_virtio_pciconfig_access_bar_offset_hwtcl Offset within BAR 0 pf4_virtio_pciconfig_access_structure_length_hwtcl Structure Length in Bytes 0 pf5_virtio_capability_present_hwtcl Enable VIRTIO Capabilities for PF5 0 pf5_virtio_device_specific_cap_present_hwtcl Enable Device Specific Capability for PF5 0 pf5_virtio_cmn_config_bar_indicator_hwtcl BAR Indicator 0 pf5_virtio_cmn_config_bar_offset_hwtcl Offset within BAR 0 pf5_virtio_cmn_config_structure_length_hwtcl Structure Length in Bytes 0 pf5_virtio_notification_bar_indicator_hwtcl BAR Indicator 0 pf5_virtio_notification_bar_offset_hwtcl Offset within BAR 0 pf5_virtio_notification_structure_length_hwtcl Structure Length in Bytes 0 pf5_virtio_notify_off_multiplier_hwtcl Notify Off Multiplier 0 pf5_virtio_isrstatus_bar_indicator_hwtcl BAR Indicator 0 pf5_virtio_isrstatus_bar_offset_hwtcl Offset within BAR 0 pf5_virtio_isrstatus_structure_length_hwtcl Structure Length in Bytes 0 pf5_virtio_devspecific_bar_indicator_hwtcl BAR Indicator 0 pf5_virtio_devspecific_bar_offset_hwtcl Offset within BAR 0 pf5_virtio_devspecific_structure_length_hwtcl Structure Length in Bytes 0 pf5_virtio_pciconfig_access_bar_indicator_hwtcl BAR Indicator 0 pf5_virtio_pciconfig_access_bar_offset_hwtcl Offset within BAR 0 pf5_virtio_pciconfig_access_structure_length_hwtcl Structure Length in Bytes 0 pf6_virtio_capability_present_hwtcl Enable VIRTIO Capabilities for PF6 0 pf6_virtio_device_specific_cap_present_hwtcl Enable Device Specific Capability for PF6 0 pf6_virtio_cmn_config_bar_indicator_hwtcl BAR Indicator 0 pf6_virtio_cmn_config_bar_offset_hwtcl Offset within BAR 0 pf6_virtio_cmn_config_structure_length_hwtcl Structure Length in Bytes 0 pf6_virtio_notification_bar_indicator_hwtcl BAR Indicator 0 pf6_virtio_notification_bar_offset_hwtcl Offset within BAR 0 pf6_virtio_notification_structure_length_hwtcl Structure Length in Bytes 0 pf6_virtio_notify_off_multiplier_hwtcl Notify Off Multiplier 0 pf6_virtio_isrstatus_bar_indicator_hwtcl BAR Indicator 0 pf6_virtio_isrstatus_bar_offset_hwtcl Offset within BAR 0 pf6_virtio_isrstatus_structure_length_hwtcl Structure Length in Bytes 0 pf6_virtio_devspecific_bar_indicator_hwtcl BAR Indicator 0 pf6_virtio_devspecific_bar_offset_hwtcl Offset within BAR 0 pf6_virtio_devspecific_structure_length_hwtcl Structure Length in Bytes 0 pf6_virtio_pciconfig_access_bar_indicator_hwtcl BAR Indicator 0 pf6_virtio_pciconfig_access_bar_offset_hwtcl Offset within BAR 0 pf6_virtio_pciconfig_access_structure_length_hwtcl Structure Length in Bytes 0 pf7_virtio_capability_present_hwtcl Enable VIRTIO Capabilities for PF7 0 pf7_virtio_device_specific_cap_present_hwtcl Enable Device Specific Capability for PF7 0 pf7_virtio_cmn_config_bar_indicator_hwtcl BAR Indicator 0 pf7_virtio_cmn_config_bar_offset_hwtcl Offset within BAR 0 pf7_virtio_cmn_config_structure_length_hwtcl Structure Length in Bytes 0 pf7_virtio_notification_bar_indicator_hwtcl BAR Indicator 0 pf7_virtio_notification_bar_offset_hwtcl Offset within BAR 0 pf7_virtio_notification_structure_length_hwtcl Structure Length in Bytes 0 pf7_virtio_notify_off_multiplier_hwtcl Notify Off Multiplier 0 pf7_virtio_isrstatus_bar_indicator_hwtcl BAR Indicator 0 pf7_virtio_isrstatus_bar_offset_hwtcl Offset within BAR 0 pf7_virtio_isrstatus_structure_length_hwtcl Structure Length in Bytes 0 pf7_virtio_devspecific_bar_indicator_hwtcl BAR Indicator 0 pf7_virtio_devspecific_bar_offset_hwtcl Offset within BAR 0 pf7_virtio_devspecific_structure_length_hwtcl Structure Length in Bytes 0 pf7_virtio_pciconfig_access_bar_indicator_hwtcl BAR Indicator 0 pf7_virtio_pciconfig_access_bar_offset_hwtcl Offset within BAR 0 pf7_virtio_pciconfig_access_structure_length_hwtcl Structure Length in Bytes 0 pf0vf_virtio_capability_present_hwtcl Enable VIRTIO Capabilities for PF0 VFs 0 pf0vf_virtio_device_specific_cap_present_hwtcl Enable Device Specific Capability for PF0 VFs 0 pf0vf_virtio_cmn_config_bar_indicator_hwtcl BAR Indicator 0 pf0vf_virtio_cmn_config_bar_offset_hwtcl Offset within BAR 0 pf0vf_virtio_cmn_config_structure_length_hwtcl Structure Length in Bytes 0 pf0vf_virtio_notification_bar_indicator_hwtcl BAR Indicator 0 pf0vf_virtio_notification_bar_offset_hwtcl Offset within BAR 0 pf0vf_virtio_notification_structure_length_hwtcl Structure Length in Bytes 0 pf0vf_virtio_notify_off_multiplier_hwtcl Notify Off Multiplier 0 pf0vf_virtio_isrstatus_bar_indicator_hwtcl BAR Indicator 0 pf0vf_virtio_isrstatus_bar_offset_hwtcl Offset within BAR 0 pf0vf_virtio_isrstatus_structure_length_hwtcl Structure Length in Bytes 0 pf0vf_virtio_devspecific_bar_indicator_hwtcl BAR Indicator 0 pf0vf_virtio_devspecific_bar_offset_hwtcl Offset within BAR 0 pf0vf_virtio_devspecific_structure_length_hwtcl Structure Length in Bytes 0 pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl BAR Indicator 0 pf0vf_virtio_pciconfig_access_bar_offset_hwtcl Offset within BAR 0 pf0vf_virtio_pciconfig_access_structure_length_hwtcl Structure Length in Bytes 0 pf1vf_virtio_capability_present_hwtcl Enable VIRTIO Capabilities for PF1 VFs 0 pf1vf_virtio_device_specific_cap_present_hwtcl Enable Device Specific Capability for PF1 VFs 0 pf1vf_virtio_cmn_config_bar_indicator_hwtcl BAR Indicator 0 pf1vf_virtio_cmn_config_bar_offset_hwtcl Offset within BAR 0 pf1vf_virtio_cmn_config_structure_length_hwtcl Structure Length in Bytes 0 pf1vf_virtio_notification_bar_indicator_hwtcl BAR Indicator 0 pf1vf_virtio_notification_bar_offset_hwtcl Offset within BAR 0 pf1vf_virtio_notification_structure_length_hwtcl Structure Length in Bytes 0 pf1vf_virtio_notify_off_multiplier_hwtcl Notify Off Multiplier 0 pf1vf_virtio_isrstatus_bar_indicator_hwtcl BAR Indicator 0 pf1vf_virtio_isrstatus_bar_offset_hwtcl Offset within BAR 0 pf1vf_virtio_isrstatus_structure_length_hwtcl Structure Length in Bytes 0 pf1vf_virtio_devspecific_bar_indicator_hwtcl BAR Indicator 0 pf1vf_virtio_devspecific_bar_offset_hwtcl Offset within BAR 0 pf1vf_virtio_devspecific_structure_length_hwtcl Structure Length in Bytes 0 pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl BAR Indicator 0 pf1vf_virtio_pciconfig_access_bar_offset_hwtcl Offset within BAR 0 pf1vf_virtio_pciconfig_access_structure_length_hwtcl Structure Length in Bytes 0 pf2vf_virtio_capability_present_hwtcl Enable VIRTIO Capabilities for PF2 VFs 0 pf2vf_virtio_device_specific_cap_present_hwtcl Enable Device Specific Capability for PF2 VFs 0 pf2vf_virtio_cmn_config_bar_indicator_hwtcl BAR Indicator 0 pf2vf_virtio_cmn_config_bar_offset_hwtcl Offset within BAR 0 pf2vf_virtio_cmn_config_structure_length_hwtcl Structure Length in Bytes 0 pf2vf_virtio_notification_bar_indicator_hwtcl BAR Indicator 0 pf2vf_virtio_notification_bar_offset_hwtcl Offset within BAR 0 pf2vf_virtio_notification_structure_length_hwtcl Structure Length in Bytes 0 pf2vf_virtio_notify_off_multiplier_hwtcl Notify Off Multiplier 0 pf2vf_virtio_isrstatus_bar_indicator_hwtcl BAR Indicator 0 pf2vf_virtio_isrstatus_bar_offset_hwtcl Offset within BAR 0 pf2vf_virtio_isrstatus_structure_length_hwtcl Structure Length in Bytes 0 pf2vf_virtio_devspecific_bar_indicator_hwtcl BAR Indicator 0 pf2vf_virtio_devspecific_bar_offset_hwtcl Offset within BAR 0 pf2vf_virtio_devspecific_structure_length_hwtcl Structure Length in Bytes 0 pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl BAR Indicator 0 pf2vf_virtio_pciconfig_access_bar_offset_hwtcl Offset within BAR 0 pf2vf_virtio_pciconfig_access_structure_length_hwtcl Structure Length in Bytes 0 pf3vf_virtio_capability_present_hwtcl Enable VIRTIO Capabilities for PF3 VFs 0 pf3vf_virtio_device_specific_cap_present_hwtcl Enable Device Specific Capability for PF3 VFs 0 pf3vf_virtio_cmn_config_bar_indicator_hwtcl BAR Indicator 0 pf3vf_virtio_cmn_config_bar_offset_hwtcl Offset within BAR 0 pf3vf_virtio_cmn_config_structure_length_hwtcl Structure Length in Bytes 0 pf3vf_virtio_notification_bar_indicator_hwtcl BAR Indicator 0 pf3vf_virtio_notification_bar_offset_hwtcl Offset within BAR 0 pf3vf_virtio_notification_structure_length_hwtcl Structure Length in Bytes 0 pf3vf_virtio_notify_off_multiplier_hwtcl Notify Off Multiplier 0 pf3vf_virtio_isrstatus_bar_indicator_hwtcl BAR Indicator 0 pf3vf_virtio_isrstatus_bar_offset_hwtcl Offset within BAR 0 pf3vf_virtio_isrstatus_structure_length_hwtcl Structure Length in Bytes 0 pf3vf_virtio_devspecific_bar_indicator_hwtcl BAR Indicator 0 pf3vf_virtio_devspecific_bar_offset_hwtcl Offset within BAR 0 pf3vf_virtio_devspecific_structure_length_hwtcl Structure Length in Bytes 0 pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl BAR Indicator 0 pf3vf_virtio_pciconfig_access_bar_offset_hwtcl Offset within BAR 0 pf3vf_virtio_pciconfig_access_structure_length_hwtcl Structure Length in Bytes 0 pf_tph_support_hwtcl Enable TLP Processing Hints (TPH) for PFs (0 to 3) 0 pf0_tph_int_mode_support_hwtcl Interrupt Mode 0 pf0_tph_dev_specific_mode_support_hwtcl Device Specific Mode 0 pf0_tph_st_table_location_hwtcl Steering Tag Table Location 0 pf0_tph_st_table_size_hwtcl Steering Tag Table Size 63 pf1_tph_int_mode_support_hwtcl Interrupt Mode 0 pf1_tph_dev_specific_mode_support_hwtcl Device Specific Mode 0 pf1_tph_st_table_location_hwtcl Steering Tag Table Location 0 pf1_tph_st_table_size_hwtcl Steering Tag Table Size 63 pf2_tph_int_mode_support_hwtcl Interrupt Mode 0 pf2_tph_dev_specific_mode_support_hwtcl Device Specific Mode 0 pf2_tph_st_table_location_hwtcl Steering Tag Table Location 0 pf2_tph_st_table_size_hwtcl Steering Tag Table Size 63 pf3_tph_int_mode_support_hwtcl Interrupt Mode 0 pf3_tph_dev_specific_mode_support_hwtcl Device Specific Mode 0 pf3_tph_st_table_location_hwtcl Steering Tag Table Location 0 pf3_tph_st_table_size_hwtcl Steering Tag Table Size 63 vf_tph_support_hwtcl Enable TLP Processing Hints (TPH) for VFs 0 pf0_vf_tph_int_mode_support_hwtcl Interrupt Mode 0 pf0_vf_tph_dev_specific_mode_support_hwtcl Device Specific Mode 0 pf0_vf_tph_st_table_location_hwtcl Steering Tag Table Location 0 pf0_vf_tph_st_table_size_hwtcl Steering Tag Table Size 63 pf1_vf_tph_int_mode_support_hwtcl Interrupt Mode 0 pf1_vf_tph_dev_specific_mode_support_hwtcl Device Specific Mode 0 pf1_vf_tph_st_table_location_hwtcl Steering Tag Table Location 0 pf1_vf_tph_st_table_size_hwtcl Steering Tag Table Size 63 pf2_vf_tph_int_mode_support_hwtcl Interrupt Mode 0 pf2_vf_tph_dev_specific_mode_support_hwtcl Device Specific Mode 0 pf2_vf_tph_st_table_location_hwtcl Steering Tag Table Location 0 pf2_vf_tph_st_table_size_hwtcl Steering Tag Table Size 63 pf3_vf_tph_int_mode_support_hwtcl Interrupt Mode 0 pf3_vf_tph_dev_specific_mode_support_hwtcl Device Specific Mode 0 pf3_vf_tph_st_table_location_hwtcl Steering Tag Table Location 0 pf3_vf_tph_st_table_size_hwtcl Steering Tag Table Size 63 pf_ats_support_hwtcl Enable Address Translation Services (ATS) for PFs (0 to 3) 0 pf0_ats_invalidate_queue_depth_hwtcl PF0 Maximum outstanding Invalidate requests 0 pf1_ats_invalidate_queue_depth_hwtcl PF1 Maximum outstanding Invalidate requests 0 pf2_ats_invalidate_queue_depth_hwtcl PF2 Maximum outstanding Invalidate requests 0 pf3_ats_invalidate_queue_depth_hwtcl PF3 Maximum outstanding Invalidate requests 0 vf_ats_support_hwtcl Enable Address Translation Services (ATS) for VFs 0 pf0_bar0_present_hwtcl Present 1 pf0_bar1_present_hwtcl Present 0 pf0_bar2_present_hwtcl Present 0 pf0_bar3_present_hwtcl Present 0 pf0_bar4_present_hwtcl Present 0 pf0_bar5_present_hwtcl Present 0 pf0_exprom_bar_present_hwtcl Present 0 pf0_bar0_type_hwtcl Type 1 pf0_bar2_type_hwtcl Type 1 pf0_bar4_type_hwtcl Type 1 pf0_bar0_prefetchable_hwtcl Prefetchable 1 pf0_bar1_prefetchable_hwtcl Prefetchable 1 pf0_bar2_prefetchable_hwtcl Prefetchable 1 pf0_bar3_prefetchable_hwtcl Prefetchable 1 pf0_bar4_prefetchable_hwtcl Prefetchable 1 pf0_bar5_prefetchable_hwtcl Prefetchable 1 pf0_bar0_size_hwtcl Size 12 pf0_bar1_size_hwtcl Size 12 pf0_bar2_size_hwtcl Size 12 pf0_bar3_size_hwtcl Size 12 pf0_bar4_size_hwtcl Size 12 pf0_bar5_size_hwtcl Size 12 pf0_exprom_bar_size_hwtcl Size 12 pf0_vf_bar0_present_hwtcl Present 0 pf0_vf_bar1_present_hwtcl Present 0 pf0_vf_bar2_present_hwtcl Present 0 pf0_vf_bar3_present_hwtcl Present 0 pf0_vf_bar4_present_hwtcl Present 0 pf0_vf_bar5_present_hwtcl Present 0 pf0_vf_bar0_type_hwtcl Type 1 pf0_vf_bar2_type_hwtcl Type 1 pf0_vf_bar4_type_hwtcl Type 1 pf0_vf_bar0_prefetchable_hwtcl Prefetchable 1 pf0_vf_bar1_prefetchable_hwtcl Prefetchable 1 pf0_vf_bar2_prefetchable_hwtcl Prefetchable 1 pf0_vf_bar3_prefetchable_hwtcl Prefetchable 1 pf0_vf_bar4_prefetchable_hwtcl Prefetchable 1 pf0_vf_bar5_prefetchable_hwtcl Prefetchable 1 pf0_vf_bar0_size_hwtcl Size 12 pf0_vf_bar1_size_hwtcl Size 12 pf0_vf_bar2_size_hwtcl Size 12 pf0_vf_bar3_size_hwtcl Size 12 pf0_vf_bar4_size_hwtcl Size 12 pf0_vf_bar5_size_hwtcl Size 12 pf1_bar0_present_hwtcl Present 0 pf1_bar1_present_hwtcl Present 0 pf1_bar2_present_hwtcl Present 0 pf1_bar3_present_hwtcl Present 0 pf1_bar4_present_hwtcl Present 0 pf1_bar5_present_hwtcl Present 0 pf1_exprom_bar_present_hwtcl Present 0 pf1_bar0_type_hwtcl Type 1 pf1_bar2_type_hwtcl Type 1 pf1_bar4_type_hwtcl Type 1 pf1_bar0_prefetchable_hwtcl Prefetchable 1 pf1_bar1_prefetchable_hwtcl Prefetchable 1 pf1_bar2_prefetchable_hwtcl Prefetchable 1 pf1_bar3_prefetchable_hwtcl Prefetchable 1 pf1_bar4_prefetchable_hwtcl Prefetchable 1 pf1_bar5_prefetchable_hwtcl Prefetchable 1 pf1_bar0_size_hwtcl Size 12 pf1_bar1_size_hwtcl Size 12 pf1_bar2_size_hwtcl Size 12 pf1_bar3_size_hwtcl Size 12 pf1_bar4_size_hwtcl Size 12 pf1_bar5_size_hwtcl Size 12 pf1_exprom_bar_size_hwtcl Size 12 pf1_vf_bar0_present_hwtcl Present 0 pf1_vf_bar1_present_hwtcl Present 0 pf1_vf_bar2_present_hwtcl Present 0 pf1_vf_bar3_present_hwtcl Present 0 pf1_vf_bar4_present_hwtcl Present 0 pf1_vf_bar5_present_hwtcl Present 0 pf1_vf_bar0_type_hwtcl Type 1 pf1_vf_bar2_type_hwtcl Type 1 pf1_vf_bar4_type_hwtcl Type 1 pf1_vf_bar0_prefetchable_hwtcl Prefetchable 1 pf1_vf_bar1_prefetchable_hwtcl Prefetchable 1 pf1_vf_bar2_prefetchable_hwtcl Prefetchable 1 pf1_vf_bar3_prefetchable_hwtcl Prefetchable 1 pf1_vf_bar4_prefetchable_hwtcl Prefetchable 1 pf1_vf_bar5_prefetchable_hwtcl Prefetchable 1 pf1_vf_bar0_size_hwtcl Size 12 pf1_vf_bar1_size_hwtcl size 12 pf1_vf_bar2_size_hwtcl Size 12 pf1_vf_bar3_size_hwtcl Size 12 pf1_vf_bar4_size_hwtcl Size 12 pf1_vf_bar5_size_hwtcl Size 12 pf2_bar0_present_hwtcl Present 0 pf2_bar1_present_hwtcl Present 0 pf2_bar2_present_hwtcl Present 0 pf2_bar3_present_hwtcl Present 0 pf2_bar4_present_hwtcl Present 0 pf2_bar5_present_hwtcl Present 0 pf2_exprom_bar_present_hwtcl Present 0 pf2_bar0_type_hwtcl Type 1 pf2_bar2_type_hwtcl Type 1 pf2_bar4_type_hwtcl Type 1 pf2_bar0_prefetchable_hwtcl Prefetchable 1 pf2_bar1_prefetchable_hwtcl Prefetchable 1 pf2_bar2_prefetchable_hwtcl Prefetchable 1 pf2_bar3_prefetchable_hwtcl Prefetchable 1 pf2_bar4_prefetchable_hwtcl Prefetchable 1 pf2_bar5_prefetchable_hwtcl Prefetchable 1 pf2_bar0_size_hwtcl Size 12 pf2_bar1_size_hwtcl Size 12 pf2_bar2_size_hwtcl Size 12 pf2_bar3_size_hwtcl Size 12 pf2_bar4_size_hwtcl Size 12 pf2_bar5_size_hwtcl Size 12 pf2_exprom_bar_size_hwtcl Size 12 pf2_vf_bar0_present_hwtcl Present 0 pf2_vf_bar1_present_hwtcl Present 0 pf2_vf_bar2_present_hwtcl Present 0 pf2_vf_bar3_present_hwtcl Present 0 pf2_vf_bar4_present_hwtcl Present 0 pf2_vf_bar5_present_hwtcl Present 0 pf2_vf_bar0_type_hwtcl Type 1 pf2_vf_bar2_type_hwtcl Type 1 pf2_vf_bar4_type_hwtcl Type 1 pf2_vf_bar0_prefetchable_hwtcl Prefetchable 1 pf2_vf_bar1_prefetchable_hwtcl Prefetchable 1 pf2_vf_bar2_prefetchable_hwtcl Prefetchable 1 pf2_vf_bar3_prefetchable_hwtcl Prefetchable 1 pf2_vf_bar4_prefetchable_hwtcl Prefetchable 1 pf2_vf_bar5_prefetchable_hwtcl Prefetchable 1 pf2_vf_bar0_size_hwtcl Size 12 pf2_vf_bar1_size_hwtcl size 12 pf2_vf_bar2_size_hwtcl Size 12 pf2_vf_bar3_size_hwtcl Size 12 pf2_vf_bar4_size_hwtcl Size 12 pf2_vf_bar5_size_hwtcl Size 12 pf3_bar0_present_hwtcl Present 0 pf3_bar1_present_hwtcl Present 0 pf3_bar2_present_hwtcl Present 0 pf3_bar3_present_hwtcl Present 0 pf3_bar4_present_hwtcl Present 0 pf3_bar5_present_hwtcl Present 0 pf3_exprom_bar_present_hwtcl Present 0 pf3_bar0_type_hwtcl Type 1 pf3_bar2_type_hwtcl Type 1 pf3_bar4_type_hwtcl Type 1 pf3_bar0_prefetchable_hwtcl Prefetchable 1 pf3_bar1_prefetchable_hwtcl Prefetchable 1 pf3_bar2_prefetchable_hwtcl Prefetchable 1 pf3_bar3_prefetchable_hwtcl Prefetchable 1 pf3_bar4_prefetchable_hwtcl Prefetchable 1 pf3_bar5_prefetchable_hwtcl Prefetchable 1 pf3_bar0_size_hwtcl Size 12 pf3_bar1_size_hwtcl Size 12 pf3_bar2_size_hwtcl Size 12 pf3_bar3_size_hwtcl Size 12 pf3_bar4_size_hwtcl Size 12 pf3_bar5_size_hwtcl Size 12 pf3_exprom_bar_size_hwtcl Size 12 pf3_vf_bar0_present_hwtcl Present 0 pf3_vf_bar1_present_hwtcl Present 0 pf3_vf_bar2_present_hwtcl Present 0 pf3_vf_bar3_present_hwtcl Present 0 pf3_vf_bar4_present_hwtcl Present 0 pf3_vf_bar5_present_hwtcl Present 0 pf3_vf_bar0_type_hwtcl Type 1 pf3_vf_bar2_type_hwtcl Type 1 pf3_vf_bar4_type_hwtcl Type 1 pf3_vf_bar0_prefetchable_hwtcl Prefetchable 1 pf3_vf_bar1_prefetchable_hwtcl Prefetchable 1 pf3_vf_bar2_prefetchable_hwtcl Prefetchable 1 pf3_vf_bar3_prefetchable_hwtcl Prefetchable 1 pf3_vf_bar4_prefetchable_hwtcl Prefetchable 1 pf3_vf_bar5_prefetchable_hwtcl Prefetchable 1 pf3_vf_bar0_size_hwtcl Size 12 pf3_vf_bar1_size_hwtcl size 12 pf3_vf_bar2_size_hwtcl Size 12 pf3_vf_bar3_size_hwtcl Size 12 pf3_vf_bar4_size_hwtcl Size 12 pf3_vf_bar5_size_hwtcl Size 12 pf4_bar0_present_hwtcl Present 0 pf4_bar1_present_hwtcl Present 0 pf4_bar2_present_hwtcl Present 0 pf4_bar3_present_hwtcl Present 0 pf4_bar4_present_hwtcl Present 0 pf4_bar5_present_hwtcl Present 0 pf4_exprom_bar_present_hwtcl Present 0 pf4_bar0_type_hwtcl Type 1 pf4_bar2_type_hwtcl Type 1 pf4_bar4_type_hwtcl Type 1 pf4_bar0_prefetchable_hwtcl Prefetchable 1 pf4_bar1_prefetchable_hwtcl Prefetchable 1 pf4_bar2_prefetchable_hwtcl Prefetchable 1 pf4_bar3_prefetchable_hwtcl Prefetchable 1 pf4_bar4_prefetchable_hwtcl Prefetchable 1 pf4_bar5_prefetchable_hwtcl Prefetchable 1 pf4_bar0_size_hwtcl Size 12 pf4_bar1_size_hwtcl Size 12 pf4_bar2_size_hwtcl Size 12 pf4_bar3_size_hwtcl Size 12 pf4_bar4_size_hwtcl Size 12 pf4_bar5_size_hwtcl Size 12 pf4_exprom_bar_size_hwtcl Size 12 pf5_bar0_present_hwtcl Present 0 pf5_bar1_present_hwtcl Present 0 pf5_bar2_present_hwtcl Present 0 pf5_bar3_present_hwtcl Present 0 pf5_bar4_present_hwtcl Present 0 pf5_bar5_present_hwtcl Present 0 pf5_exprom_bar_present_hwtcl Present 0 pf5_bar0_type_hwtcl Type 1 pf5_bar2_type_hwtcl Type 1 pf5_bar4_type_hwtcl Type 1 pf5_bar0_prefetchable_hwtcl Prefetchable 1 pf5_bar1_prefetchable_hwtcl Prefetchable 1 pf5_bar2_prefetchable_hwtcl Prefetchable 1 pf5_bar3_prefetchable_hwtcl Prefetchable 1 pf5_bar4_prefetchable_hwtcl Prefetchable 1 pf5_bar5_prefetchable_hwtcl Prefetchable 1 pf5_bar0_size_hwtcl Size 12 pf5_bar1_size_hwtcl Size 12 pf5_bar2_size_hwtcl Size 12 pf5_bar3_size_hwtcl Size 12 pf5_bar4_size_hwtcl Size 12 pf5_bar5_size_hwtcl Size 12 pf5_exprom_bar_size_hwtcl Size 12 pf6_bar0_present_hwtcl Present 0 pf6_bar1_present_hwtcl Present 0 pf6_bar2_present_hwtcl Present 0 pf6_bar3_present_hwtcl Present 0 pf6_bar4_present_hwtcl Present 0 pf6_bar5_present_hwtcl Present 0 pf6_exprom_bar_present_hwtcl Present 0 pf6_bar0_type_hwtcl Type 1 pf6_bar2_type_hwtcl Type 1 pf6_bar4_type_hwtcl Type 1 pf6_bar0_prefetchable_hwtcl Prefetchable 1 pf6_bar1_prefetchable_hwtcl Prefetchable 1 pf6_bar2_prefetchable_hwtcl Prefetchable 1 pf6_bar3_prefetchable_hwtcl Prefetchable 1 pf6_bar4_prefetchable_hwtcl Prefetchable 1 pf6_bar5_prefetchable_hwtcl Prefetchable 1 pf6_bar0_size_hwtcl Size 12 pf6_bar1_size_hwtcl Size 12 pf6_bar2_size_hwtcl Size 12 pf6_bar3_size_hwtcl Size 12 pf6_bar4_size_hwtcl Size 12 pf6_bar5_size_hwtcl Size 12 pf6_exprom_bar_size_hwtcl Size 12 pf7_bar0_present_hwtcl Present 0 pf7_bar1_present_hwtcl Present 0 pf7_bar2_present_hwtcl Present 0 pf7_bar3_present_hwtcl Present 0 pf7_bar4_present_hwtcl Present 0 pf7_bar5_present_hwtcl Present 0 pf7_exprom_bar_present_hwtcl Present 0 pf7_bar0_type_hwtcl Type 1 pf7_bar2_type_hwtcl Type 1 pf7_bar4_type_hwtcl Type 1 pf7_bar0_prefetchable_hwtcl Prefetchable 1 pf7_bar1_prefetchable_hwtcl Prefetchable 1 pf7_bar2_prefetchable_hwtcl Prefetchable 1 pf7_bar3_prefetchable_hwtcl Prefetchable 1 pf7_bar4_prefetchable_hwtcl Prefetchable 1 pf7_bar5_prefetchable_hwtcl Prefetchable 1 pf7_bar0_size_hwtcl Size 12 pf7_bar1_size_hwtcl Size 12 pf7_bar2_size_hwtcl Size 12 pf7_bar3_size_hwtcl Size 12 pf7_bar4_size_hwtcl Size 12 pf7_bar5_size_hwtcl Size 12 pf7_exprom_bar_size_hwtcl Size 12 pf1_vendor_id_hwtcl Vendor ID 0 pf1_device_id_hwtcl Device ID 0 pf1_vf_device_id_hwtcl VF Device ID 0 pf1_revision_id_hwtcl Revision ID 0 pf1_class_code_hwtcl Class code 0 pf1_subclass_code_hwtcl Subclass code 0 pf1_pci_prog_intfc_byte_hwtcl Programming IF code 0 pf1_subsystem_vendor_id_hwtcl Subsystem Vendor ID 0 pf1_subsystem_device_id_hwtcl Subsystem Device ID 0 pf1_vf_subsystem_device_id_hwtcl VF Subsystem Device ID 0 pf2_vendor_id_hwtcl Vendor ID 0 pf2_device_id_hwtcl Device ID 0 pf2_vf_device_id_hwtcl VF Device ID 0 pf2_revision_id_hwtcl Revision ID 0 pf2_class_code_hwtcl Class code 0 pf2_subclass_code_hwtcl Subclass code 0 pf2_pci_prog_intfc_byte_hwtcl Programming IF code 0 pf2_subsystem_vendor_id_hwtcl Subsystem Vendor ID 0 pf2_subsystem_device_id_hwtcl Subsystem Device ID 0 pf2_vf_subsystem_device_id_hwtcl VF Subsystem Device ID 0 pf3_vendor_id_hwtcl Vendor ID 0 pf3_device_id_hwtcl Device ID 0 pf3_vf_device_id_hwtcl VF Device ID 0 pf3_revision_id_hwtcl Revision ID 0 pf3_class_code_hwtcl Class code 0 pf3_subclass_code_hwtcl Subclass code 0 pf3_pci_prog_intfc_byte_hwtcl Programming IF code 0 pf3_subsystem_vendor_id_hwtcl Subsystem Vendor ID 0 pf3_subsystem_device_id_hwtcl Subsystem Device ID 0 pf3_vf_subsystem_device_id_hwtcl VF Subsystem Device ID 0 pf4_vendor_id_hwtcl Vendor ID 0 pf4_device_id_hwtcl Device ID 0 pf4_vf_device_id_hwtcl VF Device ID 0 pf4_revision_id_hwtcl Revision ID 0 pf4_class_code_hwtcl Class code 0 pf4_subclass_code_hwtcl Subclass code 0 pf4_pci_prog_intfc_byte_hwtcl Programming IF code 0 pf4_subsystem_vendor_id_hwtcl Subsystem Vendor ID 0 pf4_subsystem_device_id_hwtcl Subsystem Device ID 0 pf4_vf_subsystem_device_id_hwtcl VF Subsystem Device ID 0 pf5_vendor_id_hwtcl Vendor ID 0 pf5_device_id_hwtcl Device ID 0 pf5_vf_device_id_hwtcl VF Device ID 0 pf5_revision_id_hwtcl Revision ID 0 pf5_class_code_hwtcl Class code 0 pf5_subclass_code_hwtcl Subclass code 0 pf5_pci_prog_intfc_byte_hwtcl Programming IF code 0 pf5_subsystem_vendor_id_hwtcl Subsystem Vendor ID 0 pf5_subsystem_device_id_hwtcl Subsystem Device ID 0 pf5_vf_subsystem_device_id_hwtcl VF Subsystem Device ID 0 pf6_vendor_id_hwtcl Vendor ID 0 pf6_device_id_hwtcl Device ID 0 pf6_vf_device_id_hwtcl VF Device ID 0 pf6_revision_id_hwtcl Revision ID 0 pf6_class_code_hwtcl Class code 0 pf6_subclass_code_hwtcl Subclass code 0 pf6_pci_prog_intfc_byte_hwtcl Programming IF code 0 pf6_subsystem_vendor_id_hwtcl Subsystem Vendor ID 0 pf6_subsystem_device_id_hwtcl Subsystem Device ID 0 pf6_vf_subsystem_device_id_hwtcl VF Subsystem Device ID 0 pf7_vendor_id_hwtcl Vendor ID 0 pf7_device_id_hwtcl Device ID 0 pf7_vf_device_id_hwtcl VF Device ID 0 pf7_revision_id_hwtcl Revision ID 0 pf7_class_code_hwtcl Class code 0 pf7_subclass_code_hwtcl Subclass code 0 pf7_pci_prog_intfc_byte_hwtcl Programming IF code 0 pf7_subsystem_vendor_id_hwtcl Subsystem Vendor ID 0 pf7_subsystem_device_id_hwtcl Subsystem Device ID 0 pf7_vf_subsystem_device_id_hwtcl VF Subsystem Device ID 0 pf_msi_support_hwtcl PF MSI 0 pf0_msi_multi_message_capable_hwtcl PF0 MSI Requests 4 pf1_msi_multi_message_capable_hwtcl PF1 MSI Requests 4 pf2_msi_multi_message_capable_hwtcl PF2 MSI Requests 4 pf3_msi_multi_message_capable_hwtcl PF3 MSI Requests 4 pf4_msi_multi_message_capable_hwtcl PF4 MSI Requests 4 pf5_msi_multi_message_capable_hwtcl PF5 MSI Requests 4 pf6_msi_multi_message_capable_hwtcl PF6 MSI Requests 4 pf7_msi_multi_message_capable_hwtcl PF7 MSI Requests 4 pf_enable_function_msix_support_hwtcl PF MSI-X 0 vf_msix_cap_present_hwtcl VF MSI-X 0 pf0_msix_table_size_hwtcl Table size 0 pf0_msix_table_offset_hwtcl Table offset 0 pf0_msix_table_bir_hwtcl Table BAR indicator 0 pf0_msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 pf0_msix_pba_bir_hwtcl PBA BAR Indicator 0 pf1_msix_table_size_hwtcl Table size 0 pf1_msix_table_offset_hwtcl Table offset 0 pf1_msix_table_bir_hwtcl Table BAR indicator 0 pf1_msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 pf1_msix_pba_bir_hwtcl PBA BAR Indicator 0 pf2_msix_table_size_hwtcl Table size 0 pf2_msix_table_offset_hwtcl Table offset 0 pf2_msix_table_bir_hwtcl Table BAR indicator 0 pf2_msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 pf2_msix_pba_bir_hwtcl PBA BAR Indicator 0 pf3_msix_table_size_hwtcl Table size 0 pf3_msix_table_offset_hwtcl Table offset 0 pf3_msix_table_bir_hwtcl Table BAR indicator 0 pf3_msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 pf3_msix_pba_bir_hwtcl PBA BAR Indicator 0 pf4_msix_table_size_hwtcl Table size 0 pf4_msix_table_offset_hwtcl Table offset 0 pf4_msix_table_bir_hwtcl Table BAR indicator 0 pf4_msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 pf4_msix_pba_bir_hwtcl PBA BAR Indicator 0 pf5_msix_table_size_hwtcl Table size 0 pf5_msix_table_offset_hwtcl Table offset 0 pf5_msix_table_bir_hwtcl Table BAR indicator 0 pf5_msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 pf5_msix_pba_bir_hwtcl PBA BAR Indicator 0 pf6_msix_table_size_hwtcl Table size 0 pf6_msix_table_offset_hwtcl Table offset 0 pf6_msix_table_bir_hwtcl Table BAR indicator 0 pf6_msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 pf6_msix_pba_bir_hwtcl PBA BAR Indicator 0 pf7_msix_table_size_hwtcl Table size 0 pf7_msix_table_offset_hwtcl Table offset 0 pf7_msix_table_bir_hwtcl Table BAR indicator 0 pf7_msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 pf7_msix_pba_bir_hwtcl PBA BAR Indicator 0 pf0_vf_msix_tbl_size_hwtcl Table size 0 pf0_vf_msix_tbl_offset_hwtcl Table offset 0 pf0_vf_msix_tbl_bir_hwtcl Table BAR indicator 0 pf0_vf_msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 pf0_vf_msix_pba_bir_hwtcl PBA BAR Indicator 0 pf1_vf_msix_tbl_size_hwtcl Table size 0 pf1_vf_msix_tbl_offset_hwtcl Table offset 0 pf1_vf_msix_tbl_bir_hwtcl Table BAR indicator 0 pf1_vf_msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 pf1_vf_msix_pba_bir_hwtcl PBA BAR Indicator 0 pf2_vf_msix_tbl_size_hwtcl Table size 0 pf2_vf_msix_tbl_offset_hwtcl Table offset 0 pf2_vf_msix_tbl_bir_hwtcl Table BAR indicator 0 pf2_vf_msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 pf2_vf_msix_pba_bir_hwtcl PBA BAR Indicator 0 pf3_vf_msix_tbl_size_hwtcl Table size 0 pf3_vf_msix_tbl_offset_hwtcl Table offset 0 pf3_vf_msix_tbl_bir_hwtcl Table BAR indicator 0 pf3_vf_msix_pba_offset_hwtcl Pending bit array (PBA) offset 0 pf3_vf_msix_pba_bir_hwtcl PBA BAR Indicator 0 pf0_interrupt_pin_hwtcl PF0 Interrupt Pin inta pf1_interrupt_pin_hwtcl PF1 Interrupt Pin inta pf2_interrupt_pin_hwtcl PF2 Interrupt Pin inta pf3_interrupt_pin_hwtcl PF3 Interrupt Pin inta pf4_interrupt_pin_hwtcl PF4 Interrupt Pin inta pf5_interrupt_pin_hwtcl PF5 Interrupt Pin inta pf6_interrupt_pin_hwtcl PF6 Interrupt Pin inta pf7_interrupt_pin_hwtcl PF7 Interrupt Pin inta pf0_intr_line_hwtcl PF0 Interrupt Line 0 pf1_intr_line_hwtcl PF1 Interrupt Line 0 pf2_intr_line_hwtcl PF2 Interrupt Line 0 pf3_intr_line_hwtcl PF3 Interrupt Line 0 pf4_intr_line_hwtcl PF4 Interrupt Line 0 pf5_intr_line_hwtcl PF5 Interrupt Line 0 pf6_intr_line_hwtcl PF6 Interrupt Line 0 pf7_intr_line_hwtcl PF7 Interrupt Line 0 app_msi_addr_pf_hwtcl app_msi_addr_pf_hwtcl 64 app_msi_data_pf_hwtcl app_msi_data_pf_hwtcl 16 app_msi_mask_pf_hwtcl app_msi_mask_pf_hwtcl 32 app_msi_msg_en_pf_hwtcl app_msi_msg_en_pf_hwtcl 3 link2csr_width_hwtcl link2csr_width_hwtcl 16 lmi_width_hwtcl lmi_width_hwtcl 8 cseb_route_to_avl_rx_st_hwtcl cseb_route_to_avl_rx_st_hwtcl 0 test_cseb_switch_hwtcl test_cseb_switch_hwtcl 0 cseb_temp_busy_crs_hwtcl cseb_temp_busy_crs_hwtcl 0 message_level Message level for rule violations error rx_polinv_soft_logic_enable Enable RX polarity inversion soft logic 0 enable_soft_dfe Enable Soft DFE controller IP 0 enable_gen3phase2eq_timechange Enable Phase2 Eq Time Programming 0 gen3_coeff_3_ber_meas_hwtcl Phase2 Eq Time in Milli Seconds 12ms slave_address_map_0_hwtcl slave_address_map_0_hwtcl 0 slave_address_map_1_hwtcl slave_address_map_1_hwtcl 0 slave_address_map_2_hwtcl slave_address_map_2_hwtcl 0 slave_address_map_2_hprxm_hwtcl slave_address_map_2_hprxm_hwtcl 0 slave_address_map_3_hwtcl slave_address_map_3_hwtcl 0 slave_address_map_4_hwtcl slave_address_map_4_hwtcl 0 slave_address_map_5_hwtcl slave_address_map_5_hwtcl 0 design_environment_hwtcl design_environment_hwtcl NATIVE tlp_inspector_hwtcl Enable link Inspector 0 tlp_inspector_use_signal_probe_hwtcl tlp_inspector_use_signal_probe_hwtcl 0 tlp_inspector_use_thin_rx_master tlp_inspector_use_thin_rx_master 0 tlp_insp_trg_dw0_hwtcl tlp_insp_trg_dw0_hwtcl 2049 tlp_insp_trg_dw1_hwtcl tlp_insp_trg_dw1_hwtcl 0 tlp_insp_trg_dw2_hwtcl tlp_insp_trg_dw2_hwtcl 0 enable_ast_trs_hwtcl enable_ast_trs_hwtcl 0 ast_trs_num_desc_hwtcl ast_trs_num_desc_hwtcl 16 ast_trs_txdata_width_hwtcl ast_trs_txdata_width_hwtcl 256 ast_trs_txdesc_width_hwtcl ast_trs_txdesc_width_hwtcl 256 ast_trs_txstatus_width_hwtcl ast_trs_txstatus_width_hwtcl 256 ast_trs_rxdata_width_hwtcl ast_trs_rxdata_width_hwtcl 256 ast_trs_rxdesc_width_hwtcl ast_trs_rxdesc_width_hwtcl 256 ast_trs_txmty_width_hwtcl ast_trs_rxdesc_width_hwtcl 32 ast_trs_rxmty_width_hwtcl ast_trs_rxdesc_width_hwtcl 32 dma_use_scfifo_ext_hwtcl dma_use_scfifo_ext_hwtcl 0 use_dynamic_design_example_hwtcl use_dynamic_design_example_hwtcl 1 use_rpbfm_pro use_rpbfm_pro 0 silicon_rev silicon_rev 20nm5es hip_ac_pwr_clk_freq_in_hz hip_ac_pwr_clk_freq_in_hz 125000000 ko_compl_data ko_compl_data 440 ko_compl_header ko_compl_header 112 acknack_base acknack_base 0 acknack_set acknack_set false advance_error_reporting advance_error_reporting disable app_interface_width app_interface_width avst_64bit arb_upfc_30us_counter arb_upfc_30us_counter 0 arb_upfc_30us_en arb_upfc_30us_en enable aspm_config_management aspm_config_management true aspm_patch_disable aspm_patch_disable enable_both ast_width_rx ast_width_rx rx_64 ast_width_tx ast_width_tx tx_64 atomic_malformed atomic_malformed false atomic_op_completer_32bit atomic_op_completer_32bit false atomic_op_completer_64bit atomic_op_completer_64bit false atomic_op_routing atomic_op_routing false auto_msg_drop_enable auto_msg_drop_enable false bar0_size_mask bar0_size_mask 0 bar0_type bar0_type bar0_32bit_non_prefetch_mem bar1_size_mask bar1_size_mask 0 bar1_type bar1_type bar1_disable bar2_size_mask bar2_size_mask 0 bar2_type bar2_type bar2_64bit_prefetch_mem bar3_size_mask bar3_size_mask 0 bar3_type bar3_type bar3_disable bar4_size_mask bar4_size_mask 0 bar4_type bar4_type bar4_disable bar5_size_mask bar5_size_mask 0 bar5_type bar5_type bar5_disable base_counter_sel base_counter_sel count_clk_62p5 bist_memory_settings bist_memory_settings 2417851639246850506078208 bridge_port_ssid_support bridge_port_ssid_support false bridge_port_vga_enable bridge_port_vga_enable false bypass_cdc bypass_cdc false bypass_clk_switch bypass_clk_switch false bypass_tl bypass_tl false cas_completer_128bit cas_completer_128bit false cdc_clk_relation cdc_clk_relation plesiochronous cdc_dummy_insert_limit cdc_dummy_insert_limit 11 cfg_parchk_ena cfg_parchk_ena disable cfgbp_req_recov_disable cfgbp_req_recov_disable false class_code class_code 0 clock_pwr_management clock_pwr_management false completion_timeout completion_timeout abcd core_clk_divider core_clk_divider div_2 core_clk_freq_mhz core_clk_freq_mhz core_clk_250mhz core_clk_out_sel core_clk_out_sel core_clk_out_div_1 core_clk_sel core_clk_sel pld_clk core_clk_source core_clk_source pll_fixed_clk cseb_bar_match_checking cseb_bar_match_checking enable cseb_config_bypass cseb_config_bypass disable cseb_cpl_status_during_cvp cseb_cpl_status_during_cvp config_retry_status cseb_cpl_tag_checking cseb_cpl_tag_checking enable cseb_disable_auto_crs cseb_disable_auto_crs false cseb_extend_pci cseb_extend_pci false cseb_extend_pcie cseb_extend_pcie false cseb_min_error_checking cseb_min_error_checking false cseb_route_to_avl_rx_st cseb_route_to_avl_rx_st cseb cseb_temp_busy_crs cseb_temp_busy_crs completer_abort_tmp_busy cvp_clk_reset cvp_clk_reset false cvp_data_compressed cvp_data_compressed false cvp_data_encrypted cvp_data_encrypted false cvp_enable cvp_enable cvp_dis cvp_mode_reset cvp_mode_reset false cvp_rate_sel cvp_rate_sel full_rate d0_pme d0_pme false d1_pme d1_pme false d1_support d1_support false d2_pme d2_pme false d2_support d2_support false d3_cold_pme d3_cold_pme false d3_hot_pme d3_hot_pme false data_pack_rx data_pack_rx disable deemphasis_enable deemphasis_enable false deskew_comma deskew_comma skp_eieos_deskw device_id device_id 1 device_number device_number 0 device_specific_init device_specific_init false dft_clock_obsrv_en dft_clock_obsrv_en disable dft_clock_obsrv_sel dft_clock_obsrv_sel dft_pclk diffclock_nfts_count diffclock_nfts_count 128 dis_cplovf dis_cplovf disable dis_paritychk dis_paritychk disable disable_link_x2_support disable_link_x2_support false disable_snoop_packet disable_snoop_packet false dl_tx_check_parity_edb dl_tx_check_parity_edb disable dll_active_report_support dll_active_report_support false early_dl_up early_dl_up false ecrc_check_capable ecrc_check_capable false ecrc_gen_capable ecrc_gen_capable false egress_block_err_report_ena egress_block_err_report_ena false ei_delay_powerdown_count ei_delay_powerdown_count 10 eie_before_nfts_count eie_before_nfts_count 4 electromech_interlock electromech_interlock false en_ieiupdatefc en_ieiupdatefc false en_lane_errchk en_lane_errchk false en_phystatus_dly en_phystatus_dly false ena_ido_cpl ena_ido_cpl false ena_ido_req ena_ido_req false enable_adapter_half_rate_mode enable_adapter_half_rate_mode false enable_ch0_pclk_out enable_ch0_pclk_out pclk_central enable_ch01_pclk_out enable_ch01_pclk_out pclk_ch0 enable_completion_timeout_disable enable_completion_timeout_disable true enable_directed_spd_chng enable_directed_spd_chng false enable_function_msix_support enable_function_msix_support false enable_l0s_aspm enable_l0s_aspm false enable_l1_aspm enable_l1_aspm false enable_rx_buffer_checking enable_rx_buffer_checking false enable_rx_reordering enable_rx_reordering true enable_slot_register enable_slot_register false endpoint_l0_latency endpoint_l0_latency 0 endpoint_l1_latency endpoint_l1_latency 0 eql_rq_int_en_number eql_rq_int_en_number 0 errmgt_fcpe_patch_dis errmgt_fcpe_patch_dis enable errmgt_fep_patch_dis errmgt_fep_patch_dis enable expansion_base_address_register expansion_base_address_register 0 extend_tag_field extend_tag_field true extended_format_field extended_format_field true extended_tag_reset extended_tag_reset false fc_init_timer fc_init_timer 1024 flow_control_timeout_count flow_control_timeout_count 200 flow_control_update_count flow_control_update_count 30 flr_capability flr_capability false force_dis_to_det force_dis_to_det false force_gen1_dis force_gen1_dis false force_tx_coeff_preset_lpbk force_tx_coeff_preset_lpbk false frame_err_patch_dis frame_err_patch_dis enable func_mode func_mode enable g3_bypass_equlz g3_bypass_equlz false g3_coeff_done_tmout g3_coeff_done_tmout enable g3_deskew_char g3_deskew_char default_sdsos g3_dis_be_frm_err g3_dis_be_frm_err false g3_dn_rx_hint_eqlz_0 g3_dn_rx_hint_eqlz_0 0 g3_dn_rx_hint_eqlz_1 g3_dn_rx_hint_eqlz_1 0 g3_dn_rx_hint_eqlz_2 g3_dn_rx_hint_eqlz_2 0 g3_dn_rx_hint_eqlz_3 g3_dn_rx_hint_eqlz_3 0 g3_dn_rx_hint_eqlz_4 g3_dn_rx_hint_eqlz_4 0 g3_dn_rx_hint_eqlz_5 g3_dn_rx_hint_eqlz_5 0 g3_dn_rx_hint_eqlz_6 g3_dn_rx_hint_eqlz_6 0 g3_dn_rx_hint_eqlz_7 g3_dn_rx_hint_eqlz_7 0 g3_dn_tx_preset_eqlz_0 g3_dn_tx_preset_eqlz_0 0 g3_dn_tx_preset_eqlz_1 g3_dn_tx_preset_eqlz_1 0 g3_dn_tx_preset_eqlz_2 g3_dn_tx_preset_eqlz_2 0 g3_dn_tx_preset_eqlz_3 g3_dn_tx_preset_eqlz_3 0 g3_dn_tx_preset_eqlz_4 g3_dn_tx_preset_eqlz_4 0 g3_dn_tx_preset_eqlz_5 g3_dn_tx_preset_eqlz_5 0 g3_dn_tx_preset_eqlz_6 g3_dn_tx_preset_eqlz_6 0 g3_dn_tx_preset_eqlz_7 g3_dn_tx_preset_eqlz_7 0 g3_force_ber_max g3_force_ber_max false g3_force_ber_min g3_force_ber_min true g3_lnk_trn_rx_ts g3_lnk_trn_rx_ts false g3_ltssm_eq_dbg g3_ltssm_eq_dbg false g3_ltssm_rec_dbg g3_ltssm_rec_dbg true g3_pause_ltssm_rec_en g3_pause_ltssm_rec_en disable g3_quiesce_guarant g3_quiesce_guarant false g3_redo_equlz_dis g3_redo_equlz_dis false g3_redo_equlz_en g3_redo_equlz_en false g3_up_rx_hint_eqlz_0 g3_up_rx_hint_eqlz_0 0 g3_up_rx_hint_eqlz_1 g3_up_rx_hint_eqlz_1 0 g3_up_rx_hint_eqlz_2 g3_up_rx_hint_eqlz_2 0 g3_up_rx_hint_eqlz_3 g3_up_rx_hint_eqlz_3 0 g3_up_rx_hint_eqlz_4 g3_up_rx_hint_eqlz_4 0 g3_up_rx_hint_eqlz_5 g3_up_rx_hint_eqlz_5 0 g3_up_rx_hint_eqlz_6 g3_up_rx_hint_eqlz_6 0 g3_up_rx_hint_eqlz_7 g3_up_rx_hint_eqlz_7 0 g3_up_tx_preset_eqlz_0 g3_up_tx_preset_eqlz_0 0 g3_up_tx_preset_eqlz_1 g3_up_tx_preset_eqlz_1 0 g3_up_tx_preset_eqlz_2 g3_up_tx_preset_eqlz_2 0 g3_up_tx_preset_eqlz_3 g3_up_tx_preset_eqlz_3 0 g3_up_tx_preset_eqlz_4 g3_up_tx_preset_eqlz_4 0 g3_up_tx_preset_eqlz_5 g3_up_tx_preset_eqlz_5 0 g3_up_tx_preset_eqlz_6 g3_up_tx_preset_eqlz_6 0 g3_up_tx_preset_eqlz_7 g3_up_tx_preset_eqlz_7 0 gen123_lane_rate_mode gen123_lane_rate_mode gen1_gen2 gen2_diffclock_nfts_count gen2_diffclock_nfts_count 255 gen2_pma_pll_usage gen2_pma_pll_usage use_ffpll gen2_sameclock_nfts_count gen2_sameclock_nfts_count 255 gen3_coeff_1 gen3_coeff_1 8 gen3_coeff_1_ber_meas gen3_coeff_1_ber_meas 4 gen3_coeff_1_nxtber_less gen3_coeff_1_nxtber_less 1 gen3_coeff_1_nxtber_more gen3_coeff_1_nxtber_more 1 gen3_coeff_1_preset_hint gen3_coeff_1_preset_hint 0 gen3_coeff_1_reqber gen3_coeff_1_reqber 0 gen3_coeff_1_sel gen3_coeff_1_sel preset_1 gen3_coeff_10 gen3_coeff_10 0 gen3_coeff_10_ber_meas gen3_coeff_10_ber_meas 0 gen3_coeff_10_nxtber_less gen3_coeff_10_nxtber_less 0 gen3_coeff_10_nxtber_more gen3_coeff_10_nxtber_more 0 gen3_coeff_10_preset_hint gen3_coeff_10_preset_hint 0 gen3_coeff_10_reqber gen3_coeff_10_reqber 0 gen3_coeff_10_sel gen3_coeff_10_sel preset_10 gen3_coeff_11 gen3_coeff_11 0 gen3_coeff_11_ber_meas gen3_coeff_11_ber_meas 0 gen3_coeff_11_nxtber_less gen3_coeff_11_nxtber_less 0 gen3_coeff_11_nxtber_more gen3_coeff_11_nxtber_more 0 gen3_coeff_11_preset_hint gen3_coeff_11_preset_hint 0 gen3_coeff_11_reqber gen3_coeff_11_reqber 0 gen3_coeff_11_sel gen3_coeff_11_sel preset_11 gen3_coeff_12 gen3_coeff_12 0 gen3_coeff_12_ber_meas gen3_coeff_12_ber_meas 0 gen3_coeff_12_nxtber_less gen3_coeff_12_nxtber_less 0 gen3_coeff_12_nxtber_more gen3_coeff_12_nxtber_more 0 gen3_coeff_12_preset_hint gen3_coeff_12_preset_hint 0 gen3_coeff_12_reqber gen3_coeff_12_reqber 0 gen3_coeff_12_sel gen3_coeff_12_sel preset_12 gen3_coeff_13 gen3_coeff_13 0 gen3_coeff_13_ber_meas gen3_coeff_13_ber_meas 0 gen3_coeff_13_nxtber_less gen3_coeff_13_nxtber_less 0 gen3_coeff_13_nxtber_more gen3_coeff_13_nxtber_more 0 gen3_coeff_13_preset_hint gen3_coeff_13_preset_hint 0 gen3_coeff_13_reqber gen3_coeff_13_reqber 0 gen3_coeff_13_sel gen3_coeff_13_sel preset_13 gen3_coeff_14 gen3_coeff_14 0 gen3_coeff_14_ber_meas gen3_coeff_14_ber_meas 0 gen3_coeff_14_nxtber_less gen3_coeff_14_nxtber_less 0 gen3_coeff_14_nxtber_more gen3_coeff_14_nxtber_more 0 gen3_coeff_14_preset_hint gen3_coeff_14_preset_hint 0 gen3_coeff_14_reqber gen3_coeff_14_reqber 0 gen3_coeff_14_sel gen3_coeff_14_sel preset_14 gen3_coeff_15 gen3_coeff_15 0 gen3_coeff_15_ber_meas gen3_coeff_15_ber_meas 0 gen3_coeff_15_nxtber_less gen3_coeff_15_nxtber_less 0 gen3_coeff_15_nxtber_more gen3_coeff_15_nxtber_more 0 gen3_coeff_15_preset_hint gen3_coeff_15_preset_hint 0 gen3_coeff_15_reqber gen3_coeff_15_reqber 0 gen3_coeff_15_sel gen3_coeff_15_sel preset_15 gen3_coeff_16 gen3_coeff_16 0 gen3_coeff_16_ber_meas gen3_coeff_16_ber_meas 0 gen3_coeff_16_nxtber_less gen3_coeff_16_nxtber_less 0 gen3_coeff_16_nxtber_more gen3_coeff_16_nxtber_more 0 gen3_coeff_16_preset_hint gen3_coeff_16_preset_hint 0 gen3_coeff_16_reqber gen3_coeff_16_reqber 0 gen3_coeff_16_sel gen3_coeff_16_sel preset_16 gen3_coeff_17 gen3_coeff_17 196608 gen3_coeff_17_ber_meas gen3_coeff_17_ber_meas 0 gen3_coeff_17_nxtber_less gen3_coeff_17_nxtber_less 0 gen3_coeff_17_nxtber_more gen3_coeff_17_nxtber_more 0 gen3_coeff_17_preset_hint gen3_coeff_17_preset_hint 0 gen3_coeff_17_reqber gen3_coeff_17_reqber 0 gen3_coeff_17_sel gen3_coeff_17_sel preset_17 gen3_coeff_18 gen3_coeff_18 196609 gen3_coeff_18_ber_meas gen3_coeff_18_ber_meas 0 gen3_coeff_18_nxtber_less gen3_coeff_18_nxtber_less 0 gen3_coeff_18_nxtber_more gen3_coeff_18_nxtber_more 0 gen3_coeff_18_preset_hint gen3_coeff_18_preset_hint 0 gen3_coeff_18_reqber gen3_coeff_18_reqber 0 gen3_coeff_18_sel gen3_coeff_18_sel preset_18 gen3_coeff_19 gen3_coeff_19 196609 gen3_coeff_19_ber_meas gen3_coeff_19_ber_meas 0 gen3_coeff_19_nxtber_less gen3_coeff_19_nxtber_less 0 gen3_coeff_19_nxtber_more gen3_coeff_19_nxtber_more 0 gen3_coeff_19_preset_hint gen3_coeff_19_preset_hint 0 gen3_coeff_19_reqber gen3_coeff_19_reqber 0 gen3_coeff_19_sel gen3_coeff_19_sel preset_19 gen3_coeff_2 gen3_coeff_2 8 gen3_coeff_2_ber_meas gen3_coeff_2_ber_meas 4 gen3_coeff_2_nxtber_less gen3_coeff_2_nxtber_less 2 gen3_coeff_2_nxtber_more gen3_coeff_2_nxtber_more 2 gen3_coeff_2_preset_hint gen3_coeff_2_preset_hint 7 gen3_coeff_2_reqber gen3_coeff_2_reqber 0 gen3_coeff_2_sel gen3_coeff_2_sel preset_2 gen3_coeff_20 gen3_coeff_20 196609 gen3_coeff_20_ber_meas gen3_coeff_20_ber_meas 0 gen3_coeff_20_nxtber_less gen3_coeff_20_nxtber_less 0 gen3_coeff_20_nxtber_more gen3_coeff_20_nxtber_more 0 gen3_coeff_20_preset_hint gen3_coeff_20_preset_hint 0 gen3_coeff_20_reqber gen3_coeff_20_reqber 0 gen3_coeff_20_sel gen3_coeff_20_sel preset_20 gen3_coeff_21 gen3_coeff_21 196609 gen3_coeff_21_ber_meas gen3_coeff_21_ber_meas 0 gen3_coeff_21_nxtber_less gen3_coeff_21_nxtber_less 0 gen3_coeff_21_nxtber_more gen3_coeff_21_nxtber_more 0 gen3_coeff_21_preset_hint gen3_coeff_21_preset_hint 0 gen3_coeff_21_reqber gen3_coeff_21_reqber 0 gen3_coeff_21_sel gen3_coeff_21_sel preset_21 gen3_coeff_22 gen3_coeff_22 196609 gen3_coeff_22_ber_meas gen3_coeff_22_ber_meas 0 gen3_coeff_22_nxtber_less gen3_coeff_22_nxtber_less 7 gen3_coeff_22_nxtber_more gen3_coeff_22_nxtber_more 0 gen3_coeff_22_preset_hint gen3_coeff_22_preset_hint 0 gen3_coeff_22_reqber gen3_coeff_22_reqber 0 gen3_coeff_22_sel gen3_coeff_22_sel preset_22 gen3_coeff_23 gen3_coeff_23 196609 gen3_coeff_23_ber_meas gen3_coeff_23_ber_meas 0 gen3_coeff_23_nxtber_less gen3_coeff_23_nxtber_less 0 gen3_coeff_23_nxtber_more gen3_coeff_23_nxtber_more 0 gen3_coeff_23_preset_hint gen3_coeff_23_preset_hint 0 gen3_coeff_23_reqber gen3_coeff_23_reqber 0 gen3_coeff_23_sel gen3_coeff_23_sel preset_23 gen3_coeff_24 gen3_coeff_24 196609 gen3_coeff_24_ber_meas gen3_coeff_24_ber_meas 0 gen3_coeff_24_nxtber_less gen3_coeff_24_nxtber_less 0 gen3_coeff_24_nxtber_more gen3_coeff_24_nxtber_more 0 gen3_coeff_24_preset_hint gen3_coeff_24_preset_hint 7 gen3_coeff_24_reqber gen3_coeff_24_reqber 0 gen3_coeff_24_sel gen3_coeff_24_sel preset_24 gen3_coeff_3 gen3_coeff_3 8 gen3_coeff_3_ber_meas gen3_coeff_3_ber_meas 16 gen3_coeff_3_nxtber_less gen3_coeff_3_nxtber_less 4 gen3_coeff_3_nxtber_more gen3_coeff_3_nxtber_more 4 gen3_coeff_3_preset_hint gen3_coeff_3_preset_hint 7 gen3_coeff_3_reqber gen3_coeff_3_reqber 31 gen3_coeff_3_sel gen3_coeff_3_sel preset_3 gen3_coeff_4 gen3_coeff_4 8 gen3_coeff_4_ber_meas gen3_coeff_4_ber_meas 4 gen3_coeff_4_nxtber_less gen3_coeff_4_nxtber_less 4 gen3_coeff_4_nxtber_more gen3_coeff_4_nxtber_more 4 gen3_coeff_4_preset_hint gen3_coeff_4_preset_hint 7 gen3_coeff_4_reqber gen3_coeff_4_reqber 31 gen3_coeff_4_sel gen3_coeff_4_sel preset_4 gen3_coeff_5 gen3_coeff_5 0 gen3_coeff_5_ber_meas gen3_coeff_5_ber_meas 0 gen3_coeff_5_nxtber_less gen3_coeff_5_nxtber_less 0 gen3_coeff_5_nxtber_more gen3_coeff_5_nxtber_more 0 gen3_coeff_5_preset_hint gen3_coeff_5_preset_hint 7 gen3_coeff_5_reqber gen3_coeff_5_reqber 0 gen3_coeff_5_sel gen3_coeff_5_sel preset_5 gen3_coeff_6 gen3_coeff_6 0 gen3_coeff_6_ber_meas gen3_coeff_6_ber_meas 0 gen3_coeff_6_nxtber_less gen3_coeff_6_nxtber_less 0 gen3_coeff_6_nxtber_more gen3_coeff_6_nxtber_more 0 gen3_coeff_6_preset_hint gen3_coeff_6_preset_hint 0 gen3_coeff_6_reqber gen3_coeff_6_reqber 0 gen3_coeff_6_sel gen3_coeff_6_sel preset_6 gen3_coeff_7 gen3_coeff_7 0 gen3_coeff_7_ber_meas gen3_coeff_7_ber_meas 0 gen3_coeff_7_nxtber_less gen3_coeff_7_nxtber_less 0 gen3_coeff_7_nxtber_more gen3_coeff_7_nxtber_more 0 gen3_coeff_7_preset_hint gen3_coeff_7_preset_hint 0 gen3_coeff_7_reqber gen3_coeff_7_reqber 0 gen3_coeff_7_sel gen3_coeff_7_sel preset_7 gen3_coeff_8 gen3_coeff_8 0 gen3_coeff_8_ber_meas gen3_coeff_8_ber_meas 0 gen3_coeff_8_nxtber_less gen3_coeff_8_nxtber_less 0 gen3_coeff_8_nxtber_more gen3_coeff_8_nxtber_more 0 gen3_coeff_8_preset_hint gen3_coeff_8_preset_hint 0 gen3_coeff_8_reqber gen3_coeff_8_reqber 0 gen3_coeff_8_sel gen3_coeff_8_sel preset_8 gen3_coeff_9 gen3_coeff_9 0 gen3_coeff_9_ber_meas gen3_coeff_9_ber_meas 0 gen3_coeff_9_nxtber_less gen3_coeff_9_nxtber_less 0 gen3_coeff_9_nxtber_more gen3_coeff_9_nxtber_more 0 gen3_coeff_9_preset_hint gen3_coeff_9_preset_hint 0 gen3_coeff_9_reqber gen3_coeff_9_reqber 0 gen3_coeff_9_sel gen3_coeff_9_sel preset_9 gen3_coeff_delay_count gen3_coeff_delay_count 125 gen3_coeff_errchk gen3_coeff_errchk disable gen3_dcbal_en gen3_dcbal_en true gen3_diffclock_nfts_count gen3_diffclock_nfts_count 128 gen3_force_local_coeff gen3_force_local_coeff false gen3_full_swing gen3_full_swing 60 gen3_half_swing gen3_half_swing false gen3_low_freq gen3_low_freq 20 gen3_paritychk gen3_paritychk disable gen3_pl_framing_err_dis gen3_pl_framing_err_dis enable gen3_preset_coeff_1 gen3_preset_coeff_1 64320 gen3_preset_coeff_10 gen3_preset_coeff_10 3210 gen3_preset_coeff_11 gen3_preset_coeff_11 84480 gen3_preset_coeff_2 gen3_preset_coeff_2 44160 gen3_preset_coeff_3 gen3_preset_coeff_3 52224 gen3_preset_coeff_4 gen3_preset_coeff_4 36096 gen3_preset_coeff_5 gen3_preset_coeff_5 3840 gen3_preset_coeff_6 gen3_preset_coeff_6 3462 gen3_preset_coeff_7 gen3_preset_coeff_7 3336 gen3_preset_coeff_8 gen3_preset_coeff_8 51846 gen3_preset_coeff_9 gen3_preset_coeff_9 35592 gen3_reset_eieos_cnt_bit gen3_reset_eieos_cnt_bit false gen3_rxfreqlock_counter gen3_rxfreqlock_counter 0 gen3_sameclock_nfts_count gen3_sameclock_nfts_count 128 gen3_scrdscr_bypass gen3_scrdscr_bypass true gen3_skip_ph2_ph3 gen3_skip_ph2_ph3 false hard_reset_bypass hard_reset_bypass false hard_rst_sig_chnl_en hard_rst_sig_chnl_en enable_hrc_sig_x4 hard_rst_tx_pll_rst_chnl_en hard_rst_tx_pll_rst_chnl_en enable_hrc_txpll_rst_ch4 hip_base_address hip_base_address 0 hip_clock_dis hip_clock_dis enable_hip_clk hip_hard_reset hip_hard_reset enable hip_pcs_sig_chnl_en hip_pcs_sig_chnl_en enable_hip_pcs_sig_x4 hot_plug_support hot_plug_support 0 hrc_chnl_txpll_master_cgb_rst_select hrc_chnl_txpll_master_cgb_rst_select ch3_master_cgb_sel hrdrstctrl_en hrdrstctrl_en hrdrstctrl_en iei_enable_settings iei_enable_settings gen3_infei_infsd_gen2_infsd_gen1_infsd_sd indicator indicator 0 intel_id_access intel_id_access false interrupt_pin interrupt_pin inta io_window_addr_width io_window_addr_width none jtag_id jtag_id 0 l0_exit_latency_diffclock l0_exit_latency_diffclock 6 l0_exit_latency_sameclock l0_exit_latency_sameclock 6 l01_entry_latency l01_entry_latency 31 l0s_adj_rply_timer_dis l0s_adj_rply_timer_dis enable l1_exit_latency_diffclock l1_exit_latency_diffclock 0 l1_exit_latency_sameclock l1_exit_latency_sameclock 0 l2_async_logic l2_async_logic disable lane_mask lane_mask ln_mask_x4 lane_rate lane_rate gen2 link_width link_width x4 low_priority_vc low_priority_vc single_vc_low_pr ltr_mechanism ltr_mechanism false ltssm_1ms_timeout ltssm_1ms_timeout disable ltssm_freqlocked_check ltssm_freqlocked_check disable malformed_tlp_truncate_en malformed_tlp_truncate_en disable max_link_width max_link_width x4_link_width max_payload_size max_payload_size payload_256 maximum_current maximum_current 0 millisecond_cycle_count millisecond_cycle_count 248496 msi_64bit_addressing_capable msi_64bit_addressing_capable true msi_masking_capable msi_masking_capable false msi_multi_message_capable msi_multi_message_capable count_1 msi_support msi_support true msix_pba_bir msix_pba_bir 0 msix_pba_offset msix_pba_offset 0 msix_table_bir msix_table_bir 0 msix_table_offset msix_table_offset 0 msix_table_size msix_table_size 0 national_inst_thru_enhance national_inst_thru_enhance false no_command_completed no_command_completed false no_soft_reset no_soft_reset false pcie_base_spec pcie_base_spec pcie_3p0 pcie_mode pcie_mode ep_native pcie_spec_1p0_compliance pcie_spec_1p0_compliance spec_1p1 pcie_spec_version pcie_spec_version v3 pclk_out_sel pclk_out_sel pclk pld_in_use_reg pld_in_use_reg false pm_latency_patch_dis pm_latency_patch_dis enable pm_txdl_patch_dis pm_txdl_patch_dis enable pme_clock pme_clock false port_link_number port_link_number 1 port_type port_type native_ep powerdown_mode powerdown_mode powerup prefetchable_mem_window_addr_width prefetchable_mem_window_addr_width prefetch_0 r2c_mask_easy r2c_mask_easy false r2c_mask_enable r2c_mask_enable false rec_frqlk_mon_en rec_frqlk_mon_en disable register_pipe_signals register_pipe_signals true retry_buffer_last_active_address retry_buffer_last_active_address 1023 retry_buffer_memory_settings retry_buffer_memory_settings 12885005388 retry_ecc_corr_mask_dis retry_ecc_corr_mask_dis enable revision_id revision_id 1 role_based_error_reporting role_based_error_reporting true rp_bug_fix_pri_sec_stat_reg rp_bug_fix_pri_sec_stat_reg 127 rpltim_base rpltim_base 16 rpltim_set rpltim_set true rstctl_ltssm_dis rstctl_ltssm_dis false rstctrl_1ms_count_fref_clk rstctrl_1ms_count_fref_clk 100000 rstctrl_1us_count_fref_clk rstctrl_1us_count_fref_clk 100 rstctrl_altpe3_crst_n_inv rstctrl_altpe3_crst_n_inv false rstctrl_altpe3_rst_n_inv rstctrl_altpe3_rst_n_inv false rstctrl_altpe3_srst_n_inv rstctrl_altpe3_srst_n_inv false rstctrl_chnl_cal_done_select rstctrl_chnl_cal_done_select ch0123_out_chnl_cal_done rstctrl_debug_en rstctrl_debug_en false rstctrl_force_inactive_rst rstctrl_force_inactive_rst false rstctrl_fref_clk_select rstctrl_fref_clk_select ch0_sel rstctrl_hard_block_enable rstctrl_hard_block_enable hard_rst_ctl rstctrl_hip_ep rstctrl_hip_ep hip_ep rstctrl_mask_tx_pll_lock_select rstctrl_mask_tx_pll_lock_select ch3_sel_mask_tx_pll_lock rstctrl_perst_enable rstctrl_perst_enable level rstctrl_perstn_select rstctrl_perstn_select perstn_pin rstctrl_pld_clr rstctrl_pld_clr true rstctrl_pll_cal_done_select rstctrl_pll_cal_done_select ch4_sel_pll_cal_done rstctrl_rx_pcs_rst_n_inv rstctrl_rx_pcs_rst_n_inv false rstctrl_rx_pcs_rst_n_select rstctrl_rx_pcs_rst_n_select ch0123_out_rx_pcs_rst rstctrl_rx_pll_freq_lock_select rstctrl_rx_pll_freq_lock_select not_active_rx_pll_f_lock rstctrl_rx_pll_lock_select rstctrl_rx_pll_lock_select ch0123_sel_rx_pll_lock rstctrl_rx_pma_rstb_inv rstctrl_rx_pma_rstb_inv false rstctrl_rx_pma_rstb_select rstctrl_rx_pma_rstb_select ch0123_out_rx_pma_rstb rstctrl_timer_a rstctrl_timer_a 10 rstctrl_timer_a_type rstctrl_timer_a_type a_timer_fref_cycles rstctrl_timer_b rstctrl_timer_b 10 rstctrl_timer_b_type rstctrl_timer_b_type b_timer_fref_cycles rstctrl_timer_c rstctrl_timer_c 10 rstctrl_timer_c_type rstctrl_timer_c_type c_timer_fref_cycles rstctrl_timer_d rstctrl_timer_d 20 rstctrl_timer_d_type rstctrl_timer_d_type d_timer_fref_cycles rstctrl_timer_e rstctrl_timer_e 1 rstctrl_timer_e_type rstctrl_timer_e_type e_timer_fref_cycles rstctrl_timer_f rstctrl_timer_f 10 rstctrl_timer_f_type rstctrl_timer_f_type f_timer_fref_cycles rstctrl_timer_g rstctrl_timer_g 10 rstctrl_timer_g_type rstctrl_timer_g_type g_timer_fref_cycles rstctrl_timer_h rstctrl_timer_h 4 rstctrl_timer_h_type rstctrl_timer_h_type h_timer_micro_secs rstctrl_timer_i rstctrl_timer_i 20 rstctrl_timer_i_type rstctrl_timer_i_type i_timer_fref_cycles rstctrl_timer_j rstctrl_timer_j 20 rstctrl_timer_j_type rstctrl_timer_j_type j_timer_fref_cycles rstctrl_tx_lcff_pll_lock_select rstctrl_tx_lcff_pll_lock_select ch4_sel_lcff_pll_lock rstctrl_tx_lcff_pll_rstb_select rstctrl_tx_lcff_pll_rstb_select ch4_out_lcff_pll_rstb rstctrl_tx_pcs_rst_n_inv rstctrl_tx_pcs_rst_n_inv false rstctrl_tx_pcs_rst_n_select rstctrl_tx_pcs_rst_n_select ch0123_out_tx_pcs_rst rstctrl_tx_pma_rstb_inv rstctrl_tx_pma_rstb_inv false rstctrl_tx_pma_syncp_inv rstctrl_tx_pma_syncp_inv false rstctrl_tx_pma_syncp_select rstctrl_tx_pma_syncp_select ch3_out_tx_pma_syncp rx_ast_parity rx_ast_parity disable rx_buffer_credit_alloc rx_buffer_credit_alloc balance rx_buffer_fc_protect rx_buffer_fc_protect 68 rx_buffer_protect rx_buffer_protect 68 rx_cdc_almost_empty rx_cdc_almost_empty 3 rx_cdc_almost_full rx_cdc_almost_full 12 rx_cred_ctl_param rx_cred_ctl_param disable rx_ei_l0s rx_ei_l0s disable rx_l0s_count_idl rx_l0s_count_idl 0 rx_ptr0_nonposted_dpram_max rx_ptr0_nonposted_dpram_max 2047 rx_ptr0_nonposted_dpram_min rx_ptr0_nonposted_dpram_min 1928 rx_ptr0_posted_dpram_max rx_ptr0_posted_dpram_max 1927 rx_ptr0_posted_dpram_min rx_ptr0_posted_dpram_min 0 rx_runt_patch_dis rx_runt_patch_dis enable rx_sop_ctrl rx_sop_ctrl rx_sop_boundary_64 rx_trunc_patch_dis rx_trunc_patch_dis enable rx_use_prst rx_use_prst true rx_use_prst_ep rx_use_prst_ep true rxbuf_ecc_corr_mask_dis rxbuf_ecc_corr_mask_dis enable sameclock_nfts_count sameclock_nfts_count 128 sel_enable_pcs_rx_fifo_err sel_enable_pcs_rx_fifo_err disable_sel sim_mode sim_mode disable simple_ro_fifo_control_en simple_ro_fifo_control_en disable single_rx_detect single_rx_detect detect_lane0_3 skp_os_gen3_count skp_os_gen3_count 0 skp_os_schedule_count skp_os_schedule_count 0 slot_number slot_number 0 slot_power_limit slot_power_limit 0 slot_power_scale slot_power_scale 0 slotclk_cfg slotclk_cfg static_slotclkcfgon ssid ssid 0 ssvid ssvid 0 subsystem_device_id subsystem_device_id 0 subsystem_vendor_id subsystem_vendor_id 0 sup_mode sup_mode user_mode surprise_down_error_support surprise_down_error_support false tl_cfg_div tl_cfg_div cfg_clk_div_7 tl_tx_check_parity_msg tl_tx_check_parity_msg disable tph_completer tph_completer false tx_ast_parity tx_ast_parity disable tx_cdc_almost_empty tx_cdc_almost_empty 5 tx_cdc_almost_full tx_cdc_almost_full 11 tx_sop_ctrl tx_sop_ctrl boundary_64 tx_swing tx_swing 0 txdl_fair_arbiter_counter txdl_fair_arbiter_counter 0 txdl_fair_arbiter_en txdl_fair_arbiter_en enable txrate_adv txrate_adv capability uc_calibration_en uc_calibration_en uc_calibration_en use_aer use_aer false use_crc_forwarding use_crc_forwarding false user_id user_id 0 vc_arbitration vc_arbitration single_vc_arb vc_enable vc_enable single_vc vc0_clk_enable vc0_clk_enable true vc0_rx_buffer_memory_settings vc0_rx_buffer_memory_settings 12885005388 vc0_rx_flow_ctrl_compl_data vc0_rx_flow_ctrl_compl_data 0 vc0_rx_flow_ctrl_compl_header vc0_rx_flow_ctrl_compl_header 0 vc0_rx_flow_ctrl_nonposted_data vc0_rx_flow_ctrl_nonposted_data 0 vc0_rx_flow_ctrl_nonposted_header vc0_rx_flow_ctrl_nonposted_header 56 vc0_rx_flow_ctrl_posted_data vc0_rx_flow_ctrl_posted_data 358 vc0_rx_flow_ctrl_posted_header vc0_rx_flow_ctrl_posted_header 50 vc1_clk_enable vc1_clk_enable false vendor_id vendor_id 4466 vsec_cap vsec_cap 0 vsec_id vsec_id 4466 wrong_device_id wrong_device_id disable not_use_k_gbl_bits not_use_k_gbl_bits not_used_k_gbl avmm_force_inter_sel_csr_ctrl avmm_force_inter_sel_csr_ctrl disable operating_voltage operating_voltage standard rxdl_bad_tlp_patch_dis rxdl_bad_tlp_patch_dis rxdlbug2_enable_both avmm_dprio_broadcast_en_csr_ctrl avmm_dprio_broadcast_en_csr_ctrl disable hip_ac_pwr_uw_per_mhz hip_ac_pwr_uw_per_mhz 1120 rxdl_bad_sop_eop_filter_dis rxdl_bad_sop_eop_filter_dis rxdlbug1_enable_both rxdl_lcrc_patch_dis rxdl_lcrc_patch_dis rxdlbug3_enable_both capab_rate_rxcfg_en capab_rate_rxcfg_en disable avmm_cvp_inter_sel_csr_ctrl avmm_cvp_inter_sel_csr_ctrl disable lmi_hold_off_cfg_timer_en lmi_hold_off_cfg_timer_en disable avmm_power_iso_en_csr_ctrl avmm_power_iso_en_csr_ctrl disable eco_fb332688_dis eco_fb332688_dis false AUTO_RXM_IRQ_INTERRUPTS_USED Auto INTERRUPTS_USED -1 testbench.partner.map.hip_ctrl pcie_tb.hip_ctrl testbench.partner.map.hip_pipe pcie_tb.hip_pipe testbench.partner.map.hip_serial pcie_tb.hip_serial testbench.partner.map.npor pcie_tb.npor testbench.partner.map.refclk pcie_tb.refclk testbench.partner.pcie_tb.class altera_pcie_a10_tbed testbench.partner.pcie_tb.parameter.apps_type_hwtcl 3 testbench.partner.pcie_tb.parameter.bfm_drive_interface_clk_hwtcl 1 testbench.partner.pcie_tb.parameter.bfm_drive_interface_control_hwtcl 1 testbench.partner.pcie_tb.parameter.bfm_drive_interface_npor_hwtcl 1 testbench.partner.pcie_tb.parameter.bfm_drive_interface_pipe_hwtcl 1 testbench.partner.pcie_tb.parameter.enable_pipe32_phyip_ser_driver_hwtcl 0 testbench.partner.pcie_tb.parameter.gen123_lane_rate_mode_hwtcl Gen2 (5.0 Gbps) testbench.partner.pcie_tb.parameter.lane_mask_hwtcl x4 testbench.partner.pcie_tb.parameter.pll_refclk_freq_hwtcl 100 MHz testbench.partner.pcie_tb.parameter.port_type_hwtcl Native endpoint testbench.partner.pcie_tb.parameter.serial_sim_hwtcl 1 testbench.partner.pcie_tb.version 19.1 device Device 10CX220YF780E5G deviceFamily Device family Cyclone 10 GX deviceSpeedGrade Device Speed Grade 5 generationId Generation Id 0 bonusData bonusData bonusData { element pcie_a10_hip_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos> <entry> <key>coreclkout_hip</key> <value> <connectionPointName>coreclkout_hip</connectionPointName> <suppliedSystemInfos/> <consumedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>250000000</value> </entry> </consumedSystemInfos> </value> </entry> </connPtSystemInfos> </systemInfosDefinition> false false