Intel Corporation phy_rst_ctrl_4ch xcvr_reset_control_s10_0 19.1.1 clock clk clock clockRate Clock rate 0 externallyDriven Externally driven false ptfSchematicName PTF schematic name reset reset reset associatedClock Associated clock synchronousEdges Synchronous edges NONE tx_analogreset tx_analogreset tx_analogreset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_digitalreset tx_digitalreset tx_digitalreset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_ready tx_ready tx_ready associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output pll_locked pll_locked pll_locked associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input pll_select pll_select pll_select associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_cal_busy tx_cal_busy tx_cal_busy associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_analogreset_stat tx_analogreset_stat tx_analogreset_stat associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_digitalreset_stat tx_digitalreset_stat tx_digitalreset_stat associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_analogreset rx_analogreset rx_analogreset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_digitalreset rx_digitalreset rx_digitalreset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_ready rx_ready rx_ready associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_is_lockedtodata rx_is_lockedtodata rx_is_lockedtodata associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_cal_busy rx_cal_busy rx_cal_busy associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_analogreset_stat rx_analogreset_stat rx_analogreset_stat associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_digitalreset_stat rx_digitalreset_stat rx_digitalreset_stat associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH altera_xcvr_reset_control_s10 QUARTUS_SYNTH clock in STD_LOGIC QUARTUS_SYNTH reset in STD_LOGIC QUARTUS_SYNTH tx_analogreset out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_digitalreset out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_ready out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH pll_locked in STD_LOGIC_VECTOR QUARTUS_SYNTH pll_select in STD_LOGIC_VECTOR QUARTUS_SYNTH tx_cal_busy in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_analogreset_stat in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_digitalreset_stat in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_analogreset out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_digitalreset out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_ready out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_is_lockedtodata in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_cal_busy in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_analogreset_stat in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_digitalreset_stat in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH Intel Corporation phy_rst_ctrl_4ch altera_xcvr_reset_control_s10 19.1.1 device_family device_family Stratix 10 TILE_TYPE Tile type of Native PHY IP h_tile CHANNELS Number of transceiver channels 4 PLLS Number of TX PLLs 1 SYS_CLK_IN_MHZ Input clock frequency 250 REDUCED_SIM_TIME Use fast reset for simulation 1 ENABLE_DIGITAL_SEQ Sequence RX digital reset after TX digital reset 0 gui_split_interfaces Separate interface per channel/PLL 0 TX_PLL_ENABLE Enable TX PLL reset control 0 T_PLL_POWERDOWN pll_powerdown duration 1000 TX_ENABLE Enable TX channel reset control 1 TX_PER_CHANNEL Use separate TX reset per channel 0 TX_MANUAL_RESET TX digital reset mode 0 T_TX_ANALOGRESET tx_analogreset duration 0 T_TX_DIGITALRESET tx_digitalreset duration 20 T_PLL_LOCK_HYST pll_locked input hysteresis 0 gui_pll_cal_busy Enable pll_cal_busy input port 0 EN_PLL_CAL_BUSY EN_PLL_CAL_BUSY 0 RX_ENABLE Enable RX channel reset control 1 RX_PER_CHANNEL Use separate RX reset per channel 0 RX_MANUAL_RESET RX digital reset mode 0 T_RX_ANALOGRESET rx_analogreset duration 40 T_RX_DIGITALRESET rx_digitalreset duration 5000 l_terminate_pll l_terminate_pll 1 l_terminate_tx l_terminate_tx 0 l_terminate_rx l_terminate_rx 0 l_pll_select_split l_pll_select_split 0 l_pll_select_width l_pll_select_width 1 l_pll_select_base l_pll_select_base 1 device Device 1SX280HN2F43E2VG deviceFamily Device family Stratix 10 deviceSpeedGrade Device Speed Grade 2 generationId Generation Id 0 bonusData bonusData bonusData { element xcvr_reset_control_s10_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> false false