Intel Corporation phy_10g_4ch xcvr_native_s10_htile_0 19.2.1 tx_analogreset tx_analogreset tx_analogreset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_analogreset rx_analogreset rx_analogreset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_digitalreset tx_digitalreset tx_digitalreset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_digitalreset rx_digitalreset rx_digitalreset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_analogreset_stat tx_analogreset_stat tx_analogreset_stat associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_analogreset_stat rx_analogreset_stat rx_analogreset_stat associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_digitalreset_stat tx_digitalreset_stat tx_digitalreset_stat associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_digitalreset_stat rx_digitalreset_stat rx_digitalreset_stat associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_dll_lock tx_dll_lock tx_dll_lock associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_cal_busy tx_cal_busy tx_cal_busy associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_cal_busy rx_cal_busy rx_cal_busy associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_serial_clk0 clk tx_serial_clk0 associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_cdr_refclk0 clk rx_cdr_refclk0 associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_serial_data tx_serial_data tx_serial_data associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_serial_data rx_serial_data rx_serial_data associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_is_lockedtoref rx_is_lockedtoref rx_is_lockedtoref associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_is_lockedtodata rx_is_lockedtodata rx_is_lockedtodata associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_coreclkin clk tx_coreclkin associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_coreclkin clk rx_coreclkin associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_clkout clk tx_clkout associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_clkout clk rx_clkout associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_parallel_data tx_parallel_data tx_parallel_data associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_control tx_control tx_control associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_enh_data_valid tx_enh_data_valid tx_enh_data_valid associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_fifo_wr_en tx_fifo_wr_en tx_fifo_wr_en associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input unused_tx_parallel_data unused_tx_parallel_data unused_tx_parallel_data associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_parallel_data rx_parallel_data rx_parallel_data associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_control rx_control rx_control associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_enh_data_valid rx_enh_data_valid rx_enh_data_valid associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output unused_rx_parallel_data unused_rx_parallel_data unused_rx_parallel_data associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_bitslip rx_bitslip rx_bitslip associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_fifo_rd_en rx_fifo_rd_en rx_fifo_rd_en associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH altera_xcvr_native_s10_htile QUARTUS_SYNTH tx_analogreset in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_analogreset in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_digitalreset in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_digitalreset in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_analogreset_stat out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_analogreset_stat out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_digitalreset_stat out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_digitalreset_stat out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_dll_lock out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_cal_busy out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_cal_busy out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_serial_clk0 in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_cdr_refclk0 in STD_LOGIC QUARTUS_SYNTH tx_serial_data out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_serial_data in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_is_lockedtoref out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_is_lockedtodata out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_coreclkin in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_coreclkin in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_clkout out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_clkout out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_parallel_data in 0 255 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_control in 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_enh_data_valid in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_fifo_wr_en in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH unused_tx_parallel_data in 0 47 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_parallel_data out 0 255 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_control out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_enh_data_valid out 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH unused_rx_parallel_data out 0 51 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_bitslip in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_fifo_rd_en in 0 3 STD_LOGIC_VECTOR QUARTUS_SYNTH Intel Corporation phy_10g_4ch altera_xcvr_native_s10_htile 19.2.1 rcfg_debug rcfg_debug 0 enable_multi_profile enable_multi_profile 1 rcfg_enable Enable dynamic reconfiguration 0 enable_advanced_avmm_options enable_advanced_avmm_options 0 rcfg_jtag_enable Enable Native PHY Debug Master Endpoint 0 rcfg_separate_avmm_busy Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE 0 rcfg_enable_avmm_busy_port Enable avmm_busy port 0 set_capability_reg_enable Enable capability registers 0 set_user_identifier Set user-defined IP identifier 0 set_csr_soft_logic_enable Enable control and status registers 0 dbg_embedded_debug_enable dbg_embedded_debug_enable 0 dbg_capability_reg_enable dbg_capability_reg_enable 0 dbg_user_identifier dbg_user_identifier 0 dbg_stat_soft_logic_enable dbg_stat_soft_logic_enable 0 dbg_ctrl_soft_logic_enable dbg_ctrl_soft_logic_enable 0 rcfg_file_prefix Configuration file prefix altera_xcvr_rcfg_10 rcfg_files_as_common_package Declare SystemVerilog package file as common package file 0 rcfg_sv_file_enable Generate SystemVerilog package file 0 rcfg_h_file_enable Generate C header file 0 rcfg_txt_file_enable Generate text file 0 rcfg_mif_file_enable Generate MIF (Memory Initialize File) 0 rcfg_multi_enable Enable multiple reconfiguration profiles 0 set_rcfg_emb_strm_enable Enable embedded reconfiguration streamer 0 rcfg_emb_strm_enable rcfg_emb_strm_enable 0 rcfg_reduced_files_enable Generate reduced reconfiguration files 0 rcfg_profile_cnt Number of reconfiguration profiles 2 rcfg_profile_select Store current configuration to profile: 1 rcfg_profile_data0 rcfg_profile_data0 rcfg_profile_data1 rcfg_profile_data1 rcfg_profile_data2 rcfg_profile_data2 rcfg_profile_data3 rcfg_profile_data3 rcfg_profile_data4 rcfg_profile_data4 rcfg_profile_data5 rcfg_profile_data5 rcfg_profile_data6 rcfg_profile_data6 rcfg_profile_data7 rcfg_profile_data7 rcfg_sdc_derived_profile_data0 rcfg_sdc_derived_profile_data0 rcfg_sdc_derived_profile_data1 rcfg_sdc_derived_profile_data1 rcfg_sdc_derived_profile_data2 rcfg_sdc_derived_profile_data2 rcfg_sdc_derived_profile_data3 rcfg_sdc_derived_profile_data3 rcfg_sdc_derived_profile_data4 rcfg_sdc_derived_profile_data4 rcfg_sdc_derived_profile_data5 rcfg_sdc_derived_profile_data5 rcfg_sdc_derived_profile_data6 rcfg_sdc_derived_profile_data6 rcfg_sdc_derived_profile_data7 rcfg_sdc_derived_profile_data7 rcfg_params rcfg_params rcfg_debug,rcfg_enable,rcfg_jtag_enable,rcfg_separate_avmm_busy,rcfg_enable_avmm_busy_port,set_capability_reg_enable,set_user_identifier,set_csr_soft_logic_enable,support_mode,channel_type,protocol_mode,pma_mode,duplex_mode,channels,set_data_rate,rcfg_iface_enable,enable_simple_interface,enable_split_interface,set_enable_calibration,enable_double_rate_transfer,enable_background_cal_gui,enable_direct_reset_control,disable_reset_sequencer,disable_digital_reset_sequencer,bonded_mode,set_pcs_bonding_master,pcs_reset_sequencing_mode,manual_pcs_bonding_mode,manual_pcs_bonding_comp_cnt,manual_tx_hssi_aib_bonding_mode,manual_tx_hssi_aib_bonding_comp_cnt,manual_tx_core_aib_bonding_mode,manual_tx_core_aib_bonding_comp_cnt,manual_rx_hssi_aib_bonding_mode,manual_rx_hssi_aib_bonding_comp_cnt,manual_rx_core_aib_bonding_mode,manual_rx_core_aib_bonding_comp_cnt,manual_tx_hssi_aib_indv,manual_tx_core_aib_indv,manual_rx_hssi_aib_indv,manual_rx_core_aib_indv,tx_pma_clk_div,plls,pll_select,enable_port_tx_pma_iqtxrx_clkout,enable_port_tx_pma_elecidle,number_physical_bonding_clocks,enable_qpi_mode,enable_qpi_async_transfer,enable_port_tx_pma_qpipullup,enable_port_tx_pma_qpipulldn,enable_port_tx_pma_rxfound,enable_port_rx_pma_qpipulldn,enable_port_tx_pma_txdetectrx,cdr_refclk_cnt,cdr_refclk_select,set_cdr_refclk_freq,rx_ppm_detect_threshold,enable_port_rx_pma_iqtxrx_clkout,enable_port_rx_pma_clkslip,enable_port_rx_is_lockedtodata,enable_port_rx_is_lockedtoref,enable_ports_rx_manual_cdr_mode,enable_ports_rx_prbs,enable_port_rx_seriallpbken,std_pcs_pma_width,std_low_latency_bypass_enable,enable_hip,enable_hard_reset,set_hip_cal_en,hip_mode,hip_prot_mode,hip_channels,enable_ehip,avmm_ehip_mode,adapter_ehip_mode,std_tx_byte_ser_mode,std_rx_byte_deser_mode,std_tx_8b10b_enable,std_tx_8b10b_disp_ctrl_enable,std_rx_8b10b_enable,std_rx_rmfifo_mode,std_rx_rmfifo_pattern_n,std_rx_rmfifo_pattern_p,enable_port_rx_std_rmfifo_full,enable_port_rx_std_rmfifo_empty,pcie_rate_match,std_tx_bitslip_enable,enable_port_tx_std_bitslipboundarysel,std_rx_word_aligner_mode,std_rx_word_aligner_pattern_len,std_rx_word_aligner_pattern,std_rx_word_aligner_rknumber,std_rx_word_aligner_renumber,std_rx_word_aligner_rgnumber,std_rx_word_aligner_fast_sync_status_enable,enable_port_rx_std_wa_patternalign,enable_port_rx_std_wa_a1a2size,enable_port_rx_std_bitslipboundarysel,enable_port_rx_std_bitslip,std_tx_bitrev_enable,std_tx_byterev_enable,std_tx_polinv_enable,enable_port_tx_polinv,std_rx_bitrev_enable,enable_port_rx_std_bitrev_ena,std_rx_byterev_enable,enable_port_rx_std_byterev_ena,std_rx_polinv_enable,enable_port_rx_polinv,enable_port_rx_std_signaldetect,enable_ports_pipe_sw,enable_ports_pipe_rx_elecidle,enable_ports_pipe_hclk,enh_pcs_pma_width,enh_pld_pcs_width,enh_low_latency_enable,enh_advanced_user_mode,enh_tx_frmgen_enable,enh_tx_frmgen_mfrm_length,enh_tx_frmgen_burst_enable,enable_port_tx_enh_frame,enable_port_tx_enh_frame_diag_status,enable_port_tx_enh_frame_burst_en,enh_rx_frmsync_enable,enh_rx_frmsync_mfrm_length,enable_port_rx_enh_frame,enable_port_rx_enh_frame_lock,enable_port_rx_enh_frame_diag_status,enh_tx_crcgen_enable,enh_tx_crcerr_enable,enh_rx_crcchk_enable,enable_port_rx_enh_crc32_err,enable_port_rx_enh_highber,enable_port_rx_enh_highber_clr_cnt,enable_port_rx_enh_clr_errblk_count,enh_tx_64b66b_enable,enh_rx_64b66b_enable,enh_tx_sh_err,enh_tx_scram_enable,enh_tx_scram_seed,enh_rx_descram_enable,enh_tx_dispgen_enable,enh_rx_dispchk_enable,enh_tx_randomdispbit_enable,enh_rx_blksync_enable,enable_port_rx_enh_blk_lock,enh_tx_bitslip_enable,enh_tx_polinv_enable,enh_rx_bitslip_enable,enh_rx_polinv_enable,enable_port_tx_enh_bitslip,enable_port_rx_enh_bitslip,enh_rx_krfec_err_mark_enable,enh_rx_krfec_err_mark_type,enh_tx_krfec_burst_err_enable,enh_tx_krfec_burst_err_len,enable_port_krfec_tx_enh_frame,enable_port_krfec_rx_enh_frame,enable_port_krfec_rx_enh_frame_diag_status,pcs_direct_width,enable_tx_fast_pipeln_reg,enable_rx_fast_pipeln_reg,parallel_loopback_mode,loopback_tx_clk_sel,enable_debug_ports,tx_fifo_mode,tx_fifo_pfull,tx_fifo_pempty,enable_port_tx_fifo_full,enable_port_tx_fifo_empty,enable_port_tx_fifo_pfull,enable_port_tx_fifo_pempty,enable_port_tx_pcs_fifo_full,enable_port_tx_pcs_fifo_empty,enable_port_tx_dll_lock,rx_fifo_mode,rx_fifo_pfull,rx_fifo_pempty,rx_fifo_align_del,rx_fifo_control_del,enable_port_rx_data_valid,enable_port_rx_fifo_full,enable_port_rx_fifo_empty,enable_port_rx_fifo_pfull,enable_port_rx_fifo_pempty,enable_port_rx_fifo_del,enable_port_rx_fifo_insert,enable_port_rx_fifo_rd_en,enable_port_rx_fifo_align_clr,enable_port_rx_pcs_fifo_full,enable_port_rx_pcs_fifo_empty,tx_clkout_sel,enable_port_tx_clkout2,tx_clkout2_sel,enable_port_tx_clkout_hioint,enable_port_tx_clkout2_hioint,tx_pma_div_clkout_divider,tx_coreclkin_clock_network,tx_pcs_bonding_clock_network,rx_clkout_sel,enable_port_rx_clkout2,rx_clkout2_sel,enable_port_rx_clkout_hioint,enable_port_rx_clkout2_hioint,rx_pma_div_clkout_divider,rx_coreclkin_clock_network,osc_clk_divider,enable_port_tx_fifo_latency_adj_ena,enable_port_rx_fifo_latency_adj_ena,enable_port_latency_measurement,enable_port_clock_delay_measurement,delay_measurement_clkout_sel,delay_measurement_clkout2_sel,ovrd_tx_dv_mode,usr_tx_dv_mode,ovrd_rx_dv_mode,usr_rx_dv_mode,set_prbs_soft_logic_enable,enable_rcfg_tx_digitalreset_release_ctrl,anlg_voltage,anlg_link,enable_ports_adaptation,tx_pma_analog_mode,rx_pma_analog_mode,tx_pma_optimal_settings,tx_pma_output_swing_ctrl,tx_pma_pre_emp_sign_pre_tap_1t,tx_pma_pre_emp_switching_ctrl_pre_tap_1t,tx_pma_pre_emp_sign_1st_post_tap,tx_pma_pre_emp_switching_ctrl_1st_post_tap,tx_pma_slew_rate_ctrl,tx_pma_term_sel,tx_pma_compensation_en,rx_pma_adapt_mode,rx_pma_term_sel,rx_ctle_ac_gain,rx_ctle_eq_gain,rx_vga_dc_gain rcfg_param_labels IP Parameters rcfg_debug,Enable dynamic reconfiguration,Enable Native PHY Debug Master Endpoint,Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE,Enable avmm_busy port,Enable capability registers,Set user-defined IP identifier,Enable control and status registers,Protocol support mode,Transceiver channel type,Transceiver configuration rules,PMA configuration rules,Transceiver mode,Number of data channels,Data rate,Enable datapath and interface reconfiguration,Enable simplified data interface,Provide separate interface for each channel,Enable calibration,Enable double rate transfer mode,Enable background calibration,Enable direct reset control,Disable reset sequencer,Disable digital reset sequencer,TX channel bonding mode,PCS TX channel bonding master,PCS reset sequence,PCS TX channel bonding mode,PCS TX bonding compensation counter,TX HSSI AIB bonding mode,TX HSSI AIB compensation counter,TX Core AIB bonding mode,TX Core AIB compensation counter,RX HSSI AIB bonding mode,RX HSSI AIB compensation counter,RX Core AIB bonding mode,RX Core AIB compensation counter,TX HSSI AIB sychronous bonding setting,TX Core AIB sychronous bonding setting,RX HSSI AIB sychronous bonding setting,RX Core AIB sychronous bonding setting,TX local clock division factor,Number of TX PLL clock inputs per channel,Initial TX PLL clock input selection,Enable tx_pma_iqtxrx_clkout port,Enable tx_pma_elecidle port,Number of physical bonding clock ports to use.,Enable QPI mode,Use asynchronous QPI signals,Enable tx_pma_qpipullup port,Enable tx_pma_qpipulldn port,Enable tx_pma_rxfound port,Enable rx_pma_qpipulldn port,Enable tx_pma_txdetectrx port,Number of CDR reference clocks,Selected CDR reference clock,Selected CDR reference clock frequency,PPM detector threshold,Enable rx_pma_iqtxrx_clkout port,Enable rx_pma_clkslip port,Enable rx_is_lockedtodata port,Enable rx_is_lockedtoref port,Enable rx_set_locktodata and rx_set_locktoref ports,Enable PRBS verifier control and status ports,Enable rx_seriallpbken port,Standard PCS / PMA interface width,Enable 'Standard PCS' low latency mode,Enable PCIe hard IP support,Enable hard reset controller (HIP),Enable PCIe hard IP calibration,PCIe channel HIP mode,PCIe HIP protocol mode,Number of PCIe HIP channels,Enable Ethernet Hard IP Support,Ethernet channel AVMM HIP mode,Ethernet channel Adapter HIP mode,TX byte serializer mode,RX byte deserializer mode,Enable TX 8B/10B encoder,Enable TX 8B/10B disparity control,Enable RX 8B/10B decoder,RX rate match FIFO mode,RX rate match insert/delete -ve pattern (hex),RX rate match insert/delete +ve pattern (hex),Enable rx_std_rmfifo_full port,Enable rx_std_rmfifo_empty port,PCI Express Gen 3 rate match FIFO mode,Enable TX bitslip,Enable tx_std_bitslipboundarysel port,RX word aligner mode,RX word aligner pattern length,RX word aligner pattern (hex),Number of word alignment patterns to achieve sync,Number of invalid data words to lose sync,Number of valid data words to decrement error count,Enable fast sync status reporting for deterministic latency SM,Enable rx_std_wa_patternalign port,Enable rx_std_wa_a1a2size port,Enable rx_std_bitslipboundarysel port,Enable rx_bitslip port,Enable TX bit reversal,Enable TX byte reversal,Enable TX polarity inversion,Enable tx_polinv port,Enable RX bit reversal,Enable rx_std_bitrev_ena port,Enable RX byte reversal,Enable rx_std_byterev_ena port,Enable RX polarity inversion,Enable rx_polinv port,Enable rx_std_signaldetect port,Enable PCIe dynamic datarate switch ports,Enable PCIe electrical idle control and status ports,Enable PCIe pipe_hclk_in and pipe_hclk_out ports,Enhanced PCS / PMA interface width,FPGA fabric / Enhanced PCS interface width,Enable 'Enhanced PCS' low latency mode,Enable 'Enhanced PCS' advanced user mode,Enable Interlaken frame generator,Frame generator metaframe length,Enable frame generator burst control,Enable tx_enh_frame port,Enable tx_enh_frame_diag_status port,Enable tx_enh_frame_burst_en port,Enable Interlaken frame synchronizer,Frame synchronizer metaframe length,Enable rx_enh_frame port,Enable rx_enh_frame_lock port,Enable rx_enh_frame_diag_status port,Enable Interlaken TX CRC-32 generator,Enable Interlaken TX CRC-32 generator error insertion,Enable Interlaken RX CRC-32 checker,Enable rx_enh_crc32_err port,Enable rx_enh_highber port (10GBASE-R),Enable rx_enh_highber_clr_cnt port (10GBASE-R),Enable rx_enh_clr_errblk_count port (10GBASE-R & FEC),Enable TX 64b/66b encoder,Enable RX 64b/66b decoder,Enable TX sync header error insertion,Enable TX scrambler (10GBASE-R/Interlaken),TX scrambler seed (10GBASE-R/Interlaken),Enable RX descrambler (10GBASE-R/Interlaken),Enable Interlaken TX disparity generator,Enable Interlaken RX disparity checker,Enable Interlaken TX random disparity bit,Enable RX block synchronizer,Enable rx_enh_blk_lock port,Enable TX data bitslip,Enable TX data polarity inversion,Enable RX data bitslip,Enable RX data polarity inversion,Enable tx_enh_bitslip port,Enable rx_bitslip port,Enable RX KR-FEC error marking,Error marking type,Enable KR-FEC TX error insertion,KR-FEC TX error insertion spacing,Enable tx_enh_frame port,Enable rx_enh_frame port,Enable rx_enh_frame_diag_status port,PCS Direct interface width,Enable TX fast pipeline registers,Enable RX fast pipeline registers,Parallel loopback mode,Parallel loopback mode TX clock source selection,Enable PCS reset status ports,TX Core Interface FIFO mode,TX FIFO partially full threshold,TX FIFO partially empty threshold,Enable tx_fifo_full port,Enable tx_fifo_empty port,Enable tx_fifo_pfull port,Enable tx_fifo_pempty port,Enable tx_pcs_fifo_full port,Enable tx_pcs_fifo_empty port,Enable tx_dll_lock port,RX PCS-Core Interface FIFO mode (PCS FIFO-Core FIFO),RX FIFO partially full threshold,RX FIFO partially empty threshold,Enable RX FIFO alignment word deletion (Interlaken),Enable RX FIFO control word deletion (Interlaken),Enable rx_data_valid port,Enable rx_fifo_full port,Enable rx_fifo_empty port,Enable rx_fifo_pfull port,Enable rx_fifo_pempty port,Enable rx_fifo_del port (10GBASE-R),Enable rx_fifo_insert port (10GBASE-R),Enable rx_fifo_rd_en port,Enable rx_fifo_align_clr port (Interlaken),Enable rx_pcs_fifo_full port,Enable rx_pcs_fifo_empty port,Selected tx_clkout clock source,Enable tx_clkout2 port,Selected tx_clkout2 clock source,Enable tx_clkout_hioint port,Enable tx_clkout2_hioint port,TX pma_div_clkout division factor,Selected tx_coreclkin clock network,Selected TX PCS bonding clock network,Selected rx_clkout clock source,Enable rx_clkout2 port,Selected rx_clkout2 clock source,Enable rx_clkout_hioint port,Enable rx_clkout2_hioint port,RX pma_div_clkout division factor,Selected rx_coreclkin clock network,OSC clock division factor,Enable TX FIFO latency adjustment port,Enable RX FIFO latency adjustment port,Enable latency measurement ports,Enable clock delay measurement ports,Selected delay_measurement_clkout clock source,Selected delay_measurement_clkout2 clock source,Enable TX Data Valid Gen manual setting,Generate TX Data Valid by Core AIB FIFO,Enable RX Data Valid Rcv manual setting,Consume RX Data Valid by Core AIB FIFO,Enable prbs soft accumulators,Enable rcfg_tx_digitalreset_release_ctrl port,VCCR_GXB and VCCT_GXB supply voltage for the Transceiver,Tranceiver Link Type,Enable adaptation control ports,TX PMA analog mode rules,RX PMA analog mode rules,Use default TX PMA analog settings,Output Swing Level (VOD),Pre-Emphasis First Pre-Tap Polarity,Pre-Emphasis First Pre-Tap Magnitude,Pre-Emphasis First Post-Tap Polarity,Pre-Emphasis First Post-Tap Magnitude,Slew Rate Control,On-Chip Termination,High Speed Compensation,RX adaptation mode,RX On-chip Termination,CTLE AC Gain,CTLE EQ Gain,VGA DC Gain rcfg_param_vals0 Profile 0 rcfg_param_vals1 Profile 1 rcfg_param_vals2 Profile 2 rcfg_param_vals3 Profile 3 rcfg_param_vals4 Profile 4 rcfg_param_vals5 Profile 5 rcfg_param_vals6 Profile 6 rcfg_param_vals7 Profile 7 rcfg_sdc_derived_params rcfg_sdc_derived_params enable_multi_profile,dbg_embedded_debug_enable,dbg_capability_reg_enable,dbg_user_identifier,dbg_stat_soft_logic_enable,dbg_ctrl_soft_logic_enable,l_tx_transfer_clk_hz,l_rx_transfer_clk_hz,enable_background_cal,l_tx_fifo_transfer_mode,l_rx_fifo_transfer_mode,l_num_tx_digitalreset,l_num_rx_digitalreset,l_enable_channel_bonding,l_enable_pma_bonding,l_enable_pcs_bonding,l_tx_hssi_aib_indv,l_tx_core_aib_indv,l_rx_hssi_aib_indv,l_rx_core_aib_indv,display_std_tx_pld_adapt_width,display_std_rx_pld_adapt_width,datapath_select rcfg_sdc_derived_param_vals0 rcfg_sdc_derived_param_vals0 rcfg_sdc_derived_param_vals1 rcfg_sdc_derived_param_vals1 rcfg_sdc_derived_param_vals2 rcfg_sdc_derived_param_vals2 rcfg_sdc_derived_param_vals3 rcfg_sdc_derived_param_vals3 rcfg_sdc_derived_param_vals4 rcfg_sdc_derived_param_vals4 rcfg_sdc_derived_param_vals5 rcfg_sdc_derived_param_vals5 rcfg_sdc_derived_param_vals6 rcfg_sdc_derived_param_vals6 rcfg_sdc_derived_param_vals7 rcfg_sdc_derived_param_vals7 device_family device_family Stratix 10 device device 1SX280HN2F43E2VG base_device base_device Unknown device_die_types device_die_types HSSI_CRETE2E,MAIN_ND5 device_die_revisions device_die_revisions HSSI_CRETE2E_REVB,MAIN_ND5_REVC design_environment design_environment NATIVE device_revision device_revision 14nm5bcr2eb silicon_revision silicon_revision 14nm5bcr2eb l_tile_type l_tile_type htile message_level Message level for rule violations error reduced_reset_sim_time Use fast reset for simulation 0 support_mode Protocol support mode user_mode channel_type Transceiver channel type GX protocol_mode Transceiver configuration rules basic_enh l_protocol_mode l_protocol_mode basic_enh pma_mode PMA configuration rules basic duplex_mode Transceiver mode duplex channels Number of data channels 4 set_data_rate Data rate 10312.5 data_rate_bps data_rate_bps 10312500000 l_tx_transfer_clk_hz l_tx_transfer_clk_hz 322265624 l_rx_transfer_clk_hz l_rx_transfer_clk_hz 322265624 core_speedgrade core_speedgrade e2 xcvr_speedgrade xcvr_speedgrade e2 pcs_speedgrade pcs_speedgrade e2 core_speedgrade_no_temp core_speedgrade_no_temp 2 xcvr_speedgrade_no_temp xcvr_speedgrade_no_temp 2 rcfg_iface_enable Enable datapath and interface reconfiguration 0 enable_simple_interface Enable simplified data interface 1 enable_split_interface Provide separate interface for each channel 0 set_enable_calibration Enable calibration 1 enable_calibration enable_calibration 1 enable_channel_powerdown Enable PMA/PCS powerdown support 0 enable_transparent_pcs Enable transparent PCS 0 enable_double_rate_transfer Enable double rate transfer mode 0 enable_background_cal_gui Enable background calibration 0 enable_background_cal Enable background calibration 0 set_enable_eios_rx_protect Enable PIPE EIOS RX Protection 0 enable_eios_rx_protect Enable PIPE EIOS RX Protection 0 enable_direct_reset_control Enable direct reset control 0 disable_reset_sequencer Disable reset sequencer 0 disable_digital_reset_sequencer Disable digital reset sequencer 0 l_enable_pma_channel l_enable_pma_channel 1 l_enable_pcs_channel l_enable_pcs_channel 1 l_enable_frequency_rules l_enable_frequency_rules 1 l_tx_fifo_transfer_mode TX PCS-Core Interface FIFO transfer mode x2 l_rx_fifo_transfer_mode RX PCS-Core Interface FIFO transfer mode x2 l_num_tx_digitalreset Number of TX digital resets 1 l_num_rx_digitalreset Number of RX digital resets 1 l_release_aib_reset_first l_release_aib_reset_first 1 bonded_mode TX channel bonding mode not_bonded l_enable_channel_bonding l_enable_channel_bonding 0 l_enable_pma_bonding l_enable_pma_bonding 0 l_enable_pcs_bonding l_enable_pcs_bonding 0 set_pcs_bonding_master PCS TX channel bonding master Auto pcs_bonding_master Actual PCS TX channel bonding master 0 pcs_reset_sequencing_mode PCS reset sequence not_bonded enable_manual_bonding_settings Enable manual PCS bonding settings 0 manual_pcs_bonding_mode PCS TX channel bonding mode individual manual_pcs_bonding_comp_cnt PCS TX bonding compensation counter 0 manual_tx_hssi_aib_bonding_mode TX HSSI AIB bonding mode individual manual_tx_hssi_aib_bonding_comp_cnt TX HSSI AIB compensation counter 0 manual_tx_core_aib_bonding_mode TX Core AIB bonding mode individual manual_tx_core_aib_bonding_comp_cnt TX Core AIB compensation counter 0 manual_rx_hssi_aib_bonding_mode RX HSSI AIB bonding mode individual manual_rx_hssi_aib_bonding_comp_cnt RX HSSI AIB compensation counter 0 manual_rx_core_aib_bonding_mode RX Core AIB bonding mode individual manual_rx_core_aib_bonding_comp_cnt RX Core AIB compensation counter 0 manual_tx_hssi_aib_indv TX HSSI AIB sychronous bonding setting indv_en manual_tx_core_aib_indv TX Core AIB sychronous bonding setting indv_en manual_rx_hssi_aib_indv RX HSSI AIB sychronous bonding setting indv_en manual_rx_core_aib_indv RX Core AIB sychronous bonding setting indv_en l_tx_hssi_aib_indv l_tx_hssi_aib_indv indv_en l_tx_core_aib_indv l_tx_core_aib_indv indv_en l_rx_hssi_aib_indv l_rx_hssi_aib_indv indv_en l_rx_core_aib_indv l_rx_core_aib_indv indv_en tx_pma_clk_div TX local clock division factor 1 plls Number of TX PLL clock inputs per channel 1 pll_select Initial TX PLL clock input selection 0 enable_port_tx_pma_iqtxrx_clkout Enable tx_pma_iqtxrx_clkout port 0 enable_port_tx_pma_elecidle Enable tx_pma_elecidle port 0 number_physical_bonding_clocks Number of physical bonding clock ports to use. 1 enable_qpi_mode Enable QPI mode 0 enable_qpi_async_transfer Use asynchronous QPI signals 0 enable_port_tx_pma_qpipullup Enable tx_pma_qpipullup port 0 enable_port_tx_pma_qpipulldn Enable tx_pma_qpipulldn port 0 enable_port_tx_pma_rxfound Enable tx_pma_rxfound port 0 enable_port_rx_pma_qpipulldn Enable rx_pma_qpipulldn port 0 enable_port_tx_pma_txdetectrx Enable tx_pma_txdetectrx port 0 cdr_refclk_cnt Number of CDR reference clocks 1 cdr_refclk_select Selected CDR reference clock 0 set_cdr_refclk_freq Selected CDR reference clock frequency 644.531250 rx_ppm_detect_threshold PPM detector threshold 1000 set_cdr_refclk_receiver_detect_src set_cdr_refclk_receiver_detect_src iqclk enable_port_rx_pma_iqtxrx_clkout Enable rx_pma_iqtxrx_clkout port 0 enable_port_rx_pma_clkslip Enable rx_pma_clkslip port 0 enable_port_rx_is_lockedtodata Enable rx_is_lockedtodata port 1 enable_port_rx_is_lockedtoref Enable rx_is_lockedtoref port 1 enable_ports_rx_manual_cdr_mode Enable rx_set_locktodata and rx_set_locktoref ports 0 enable_ports_rx_prbs Enable PRBS verifier control and status ports 0 enable_port_rx_seriallpbken Enable rx_seriallpbken port 0 std_pcs_pma_width Standard PCS / PMA interface width 10 display_std_tx_pld_adapt_width FPGA fabric / Standard TX PCS interface width 10 display_std_rx_pld_adapt_width FPGA fabric / Standard RX PCS interface width 10 std_low_latency_bypass_enable Enable 'Standard PCS' low latency mode 0 enable_hip Enable PCIe hard IP support 0 l_pcs_channel_hip_en l_pcs_channel_hip_en 0 enable_hard_reset Enable hard reset controller (HIP) 0 l_pcs_channel_enable_hard_reset l_pcs_channel_enable_hard_reset 0 set_hip_cal_en Enable PCIe hard IP calibration 0 hip_cal_en hip_cal_en disable hip_mode PCIe channel HIP mode disable_hip hip_prot_mode PCIe HIP protocol mode gen1 hip_channels Number of PCIe HIP channels x1 enable_ehip Enable Ethernet Hard IP Support 0 avmm_ehip_mode Ethernet channel AVMM HIP mode disable_hip adapter_ehip_mode Ethernet channel Adapter HIP mode disable_hip std_tx_byte_ser_mode TX byte serializer mode Disabled std_rx_byte_deser_mode RX byte deserializer mode Disabled std_tx_8b10b_enable Enable TX 8B/10B encoder 0 std_tx_8b10b_disp_ctrl_enable Enable TX 8B/10B disparity control 0 std_rx_8b10b_enable Enable RX 8B/10B decoder 0 std_rx_rmfifo_mode RX rate match FIFO mode disabled std_rx_rmfifo_pattern_n RX rate match insert/delete -ve pattern (hex) 0 std_rx_rmfifo_pattern_p RX rate match insert/delete +ve pattern (hex) 0 enable_port_rx_std_rmfifo_full Enable rx_std_rmfifo_full port 0 enable_port_rx_std_rmfifo_empty Enable rx_std_rmfifo_empty port 0 pcie_rate_match PCI Express Gen 3 rate match FIFO mode Bypass std_tx_bitslip_enable Enable TX bitslip 0 enable_port_tx_std_bitslipboundarysel Enable tx_std_bitslipboundarysel port 0 std_rx_word_aligner_mode RX word aligner mode bitslip std_rx_word_aligner_pattern_len RX word aligner pattern length 7 std_rx_word_aligner_pattern RX word aligner pattern (hex) 0 std_rx_word_aligner_rknumber Number of word alignment patterns to achieve sync 3 std_rx_word_aligner_renumber Number of invalid data words to lose sync 3 std_rx_word_aligner_rgnumber Number of valid data words to decrement error count 3 std_rx_word_aligner_rvnumber Number of valid data patterns required to achieve word alignment 0 std_rx_word_aligner_fast_sync_status_enable Enable fast sync status reporting for deterministic latency SM 0 enable_port_rx_std_wa_patternalign Enable rx_std_wa_patternalign port 0 enable_port_rx_std_wa_a1a2size Enable rx_std_wa_a1a2size port 0 enable_port_rx_std_bitslipboundarysel Enable rx_std_bitslipboundarysel port 0 enable_port_rx_std_bitslip Enable rx_bitslip port 0 std_tx_bitrev_enable Enable TX bit reversal 0 std_tx_byterev_enable Enable TX byte reversal 0 std_tx_polinv_enable Enable TX polarity inversion 0 enable_port_tx_polinv Enable tx_polinv port 0 std_rx_bitrev_enable Enable RX bit reversal 0 enable_port_rx_std_bitrev_ena Enable rx_std_bitrev_ena port 0 std_rx_byterev_enable Enable RX byte reversal 0 enable_port_rx_std_byterev_ena Enable rx_std_byterev_ena port 0 std_rx_polinv_enable Enable RX polarity inversion 0 enable_port_rx_polinv Enable rx_polinv port 0 enable_port_rx_std_signaldetect Enable rx_std_signaldetect port 0 enable_ports_pipe_sw Enable PCIe dynamic datarate switch ports 0 enable_ports_pipe_rx_elecidle Enable PCIe electrical idle control and status ports 0 enable_ports_pipe_hclk Enable PCIe pipe_hclk_in and pipe_hclk_out ports 0 l_pipe_early_spd_chng l_pipe_early_spd_chng 0 enable_early_spd_chng Enable early speed change 0 early_spd_chng_t1 Delay T1 for early_spd_chng 60 early_spd_chng_t2 Pulse width T2 150 early_spd_chng_t3 Delay T3 for pipe_sw 1000 enh_pcs_pma_width Enhanced PCS / PMA interface width 64 enh_pld_pcs_width FPGA fabric / Enhanced PCS interface width 66 enh_low_latency_enable Enable 'Enhanced PCS' low latency mode 0 enh_advanced_user_mode Enable 'Enhanced PCS' advanced user mode 0 enh_tx_frmgen_enable Enable Interlaken frame generator 0 enh_tx_frmgen_mfrm_length Frame generator metaframe length 2048 enh_tx_frmgen_burst_enable Enable frame generator burst control 0 enable_port_tx_enh_frame Enable tx_enh_frame port 0 enable_port_tx_enh_frame_diag_status Enable tx_enh_frame_diag_status port 0 enable_port_tx_enh_frame_burst_en Enable tx_enh_frame_burst_en port 0 enh_rx_frmsync_enable Enable Interlaken frame synchronizer 0 enh_rx_frmsync_mfrm_length Frame synchronizer metaframe length 2048 enable_port_rx_enh_frame Enable rx_enh_frame port 0 enable_port_rx_enh_frame_lock Enable rx_enh_frame_lock port 0 enable_port_rx_enh_frame_diag_status Enable rx_enh_frame_diag_status port 0 enh_tx_crcgen_enable Enable Interlaken TX CRC-32 generator 0 enh_tx_crcerr_enable Enable Interlaken TX CRC-32 generator error insertion 0 enh_rx_crcchk_enable Enable Interlaken RX CRC-32 checker 0 enable_port_rx_enh_crc32_err Enable rx_enh_crc32_err port 0 enable_port_rx_enh_highber Enable rx_enh_highber port (10GBASE-R) 0 enable_port_rx_enh_highber_clr_cnt Enable rx_enh_highber_clr_cnt port (10GBASE-R) 0 enable_port_rx_enh_clr_errblk_count Enable rx_enh_clr_errblk_count port (10GBASE-R & FEC) 0 enh_tx_64b66b_enable Enable TX 64b/66b encoder 0 enh_rx_64b66b_enable Enable RX 64b/66b decoder 0 enh_tx_sh_err Enable TX sync header error insertion 0 enh_tx_scram_enable Enable TX scrambler (10GBASE-R/Interlaken) 0 enh_tx_scram_seed TX scrambler seed (10GBASE-R/Interlaken) 0 enh_rx_descram_enable Enable RX descrambler (10GBASE-R/Interlaken) 0 enh_tx_dispgen_enable Enable Interlaken TX disparity generator 0 enh_rx_dispchk_enable Enable Interlaken RX disparity checker 0 enh_tx_randomdispbit_enable Enable Interlaken TX random disparity bit 0 enh_rx_blksync_enable Enable RX block synchronizer 0 enable_port_rx_enh_blk_lock Enable rx_enh_blk_lock port 0 enh_tx_bitslip_enable Enable TX data bitslip 0 enh_tx_polinv_enable Enable TX data polarity inversion 0 enh_rx_bitslip_enable Enable RX data bitslip 1 enh_rx_polinv_enable Enable RX data polarity inversion 0 enable_port_tx_enh_bitslip Enable tx_enh_bitslip port 0 enable_port_rx_enh_bitslip Enable rx_bitslip port 1 enh_rx_krfec_err_mark_enable Enable RX KR-FEC error marking 0 enh_rx_krfec_err_mark_type Error marking type 10G enh_tx_krfec_burst_err_enable Enable KR-FEC TX error insertion 0 enh_tx_krfec_burst_err_len KR-FEC TX error insertion spacing 1 enable_port_krfec_tx_enh_frame Enable tx_enh_frame port 0 enable_port_krfec_rx_enh_frame Enable rx_enh_frame port 0 enable_port_krfec_rx_enh_frame_diag_status Enable rx_enh_frame_diag_status port 0 pcs_direct_width PCS Direct interface width 8 enable_tx_fast_pipeln_reg Enable TX fast pipeline registers 0 enable_rx_fast_pipeln_reg Enable RX fast pipeline registers 0 parallel_loopback_mode Parallel loopback mode disable loopback_tx_clk_sel Parallel loopback mode TX clock source selection internal_clk enable_debug_ports Enable PCS reset status ports 0 enable_advanced_user_mode Enable advanced user mode 0 l_enable_loopback_mode l_enable_loopback_mode 0 tx_fifo_mode TX Core Interface FIFO mode Basic tx_fifo_pfull TX FIFO partially full threshold 18 tx_fifo_pempty TX FIFO partially empty threshold 2 enable_port_tx_fifo_full Enable tx_fifo_full port 0 enable_port_tx_fifo_empty Enable tx_fifo_empty port 0 enable_port_tx_fifo_pfull Enable tx_fifo_pfull port 0 enable_port_tx_fifo_pempty Enable tx_fifo_pempty port 0 enable_port_tx_pcs_fifo_full Enable tx_pcs_fifo_full port 0 enable_port_tx_pcs_fifo_empty Enable tx_pcs_fifo_empty port 0 enable_port_tx_dll_lock Enable tx_dll_lock port 1 rx_fifo_mode RX PCS-Core Interface FIFO mode (PCS FIFO-Core FIFO) Phase compensation-Basic rx_fifo_pfull RX FIFO partially full threshold 50 rx_fifo_pempty RX FIFO partially empty threshold 4 rx_fifo_align_del Enable RX FIFO alignment word deletion (Interlaken) 0 rx_fifo_control_del Enable RX FIFO control word deletion (Interlaken) 0 enable_port_rx_data_valid Enable rx_data_valid port 0 enable_port_rx_fifo_full Enable rx_fifo_full port 0 enable_port_rx_fifo_empty Enable rx_fifo_empty port 0 enable_port_rx_fifo_pfull Enable rx_fifo_pfull port 0 enable_port_rx_fifo_pempty Enable rx_fifo_pempty port 0 enable_port_rx_fifo_del Enable rx_fifo_del port (10GBASE-R) 0 enable_port_rx_fifo_insert Enable rx_fifo_insert port (10GBASE-R) 0 enable_port_rx_fifo_rd_en Enable rx_fifo_rd_en port 1 enable_port_rx_fifo_align_clr Enable rx_fifo_align_clr port (Interlaken) 0 enable_port_rx_pcs_fifo_full Enable rx_pcs_fifo_full port 0 enable_port_rx_pcs_fifo_empty Enable rx_pcs_fifo_empty port 0 fifo_depth_message fifo_depth_message tx_clkout_sel Selected tx_clkout clock source pma_div_clkout enable_port_tx_clkout2 Enable tx_clkout2 port 0 tx_clkout2_sel Selected tx_clkout2 clock source pcs_clkout enable_port_tx_clkout_hioint Enable tx_clkout_hioint port 0 enable_port_tx_clkout2_hioint Enable tx_clkout2_hioint port 0 tx_pma_div_clkout_divider TX pma_div_clkout division factor 33 tx_coreclkin_clock_network Selected tx_coreclkin clock network dedicated tx_pcs_bonding_clock_network Selected TX PCS bonding clock network dedicated rx_clkout_sel Selected rx_clkout clock source pma_div_clkout enable_port_rx_clkout2 Enable rx_clkout2 port 0 rx_clkout2_sel Selected rx_clkout2 clock source pcs_clkout enable_port_rx_clkout_hioint Enable rx_clkout_hioint port 0 enable_port_rx_clkout2_hioint Enable rx_clkout2_hioint port 0 rx_pma_div_clkout_divider RX pma_div_clkout division factor 33 rx_coreclkin_clock_network Selected rx_coreclkin clock network dedicated osc_clk_divider OSC clock division factor 1 l_enable_tx_pma_div_clkout l_enable_tx_pma_div_clkout 1 l_enable_rx_pma_div_clkout l_enable_rx_pma_div_clkout 1 enable_port_tx_fifo_latency_adj_ena Enable TX FIFO latency adjustment port 0 enable_port_rx_fifo_latency_adj_ena Enable RX FIFO latency adjustment port 0 enable_port_latency_measurement Enable latency measurement ports 0 enable_port_clock_delay_measurement Enable clock delay measurement ports 0 delay_measurement_clkout_sel Selected delay_measurement_clkout clock source clock_delay_measurement_clkout delay_measurement_clkout2_sel Selected delay_measurement_clkout2 clock source clock_delay_measurement_clkout generate_docs Generate parameter documentation file 1 generate_add_hdl_instance_example Generate '_hw.tcl' 'add_hdl_instance' example file 0 validation_rule_select View validation rule for parameter enable_advanced_options enable_advanced_options 0 enable_bg_cal_debug enable_bg_cal_debug 0 disable_bg_cal disable_bg_cal 0 enable_internal_options enable_internal_options 0 enable_debug_options enable_debug_options 0 enable_physical_bonding_clocks enable_physical_bonding_clocks 0 enable_tx_coreclkin2 Enable tx_coreclkin2 port 0 enable_tx_x2_coreclkin_port enable_tx_x2_coreclkin_port 0 tx_enable tx_enable 1 datapath_select datapath_select Enhanced rx_enable rx_enable 1 l_crete_nf l_crete_nf 0 l_channels l_channels 4 l_split_iface l_split_iface 0 l_pcs_pma_width l_pcs_pma_width 64 l_tx_adapt_pcs_width l_tx_adapt_pcs_width 66 l_rx_adapt_pcs_width l_rx_adapt_pcs_width 66 l_pll_settings l_pll_settings 343.750000 {refclk 343.750000 m 15 n 1 lpfd 2 lpd 2 fvco 10312.5} 687.500000 {refclk 687.500000 m 15 n 2 lpfd 2 lpd 2 fvco 10312.5} 322.265625 {refclk 322.265625 m 16 n 1 lpfd 2 lpd 2 fvco 10312.5} 644.531250 {refclk 644.531250 m 16 n 2 lpfd 2 lpd 2 fvco 10312.5} 303.308824 {refclk 303.308824 m 17 n 1 lpfd 2 lpd 2 fvco 10312.5} 606.617647 {refclk 606.617647 m 17 n 2 lpfd 2 lpd 2 fvco 10312.5} 286.458333 {refclk 286.458333 m 18 n 1 lpfd 2 lpd 2 fvco 10312.5} 572.916667 {refclk 572.916667 m 18 n 2 lpfd 2 lpd 2 fvco 10312.5} 271.381579 {refclk 271.381579 m 19 n 1 lpfd 2 lpd 2 fvco 10312.5} 542.763158 {refclk 542.763158 m 19 n 2 lpfd 2 lpd 2 fvco 10312.5} 257.812500 {refclk 257.812500 m 20 n 1 lpfd 2 lpd 2 fvco 10312.5} 515.625000 {refclk 515.625000 m 20 n 2 lpfd 2 lpd 2 fvco 10312.5} 245.535714 {refclk 245.535714 m 21 n 1 lpfd 2 lpd 2 fvco 10312.5} 491.071429 {refclk 491.071429 m 21 n 2 lpfd 2 lpd 2 fvco 10312.5} 234.375000 {refclk 234.375000 m 22 n 1 lpfd 2 lpd 2 fvco 10312.5} 468.750000 {refclk 468.750000 m 22 n 2 lpfd 2 lpd 2 fvco 10312.5} 224.184783 {refclk 224.184783 m 23 n 1 lpfd 2 lpd 2 fvco 10312.5} 448.369565 {refclk 448.369565 m 23 n 2 lpfd 2 lpd 2 fvco 10312.5} 214.843750 {refclk 214.843750 m 24 n 1 lpfd 2 lpd 2 fvco 10312.5} 429.687500 {refclk 429.687500 m 24 n 2 lpfd 2 lpd 2 fvco 10312.5} 206.250000 {refclk 206.250000 m 25 n 1 lpfd 2 lpd 2 fvco 10312.5} 412.500000 {refclk 412.500000 m 25 n 2 lpfd 2 lpd 2 fvco 10312.5} 198.317308 {refclk 198.317308 m 26 n 1 lpfd 2 lpd 2 fvco 10312.5} 396.634615 {refclk 396.634615 m 26 n 2 lpfd 2 lpd 2 fvco 10312.5} 793.269231 {refclk 793.269231 m 26 n 4 lpfd 2 lpd 2 fvco 10312.5} 190.972222 {refclk 190.972222 m 27 n 1 lpfd 2 lpd 2 fvco 10312.5} 381.944444 {refclk 381.944444 m 27 n 2 lpfd 2 lpd 2 fvco 10312.5} 763.888889 {refclk 763.888889 m 27 n 4 lpfd 2 lpd 2 fvco 10312.5} 184.151786 {refclk 184.151786 m 28 n 1 lpfd 2 lpd 2 fvco 10312.5} 368.303571 {refclk 368.303571 m 28 n 2 lpfd 2 lpd 2 fvco 10312.5} 736.607143 {refclk 736.607143 m 28 n 4 lpfd 2 lpd 2 fvco 10312.5} 177.801724 {refclk 177.801724 m 29 n 1 lpfd 2 lpd 2 fvco 10312.5} 355.603448 {refclk 355.603448 m 29 n 2 lpfd 2 lpd 2 fvco 10312.5} 711.206897 {refclk 711.206897 m 29 n 4 lpfd 2 lpd 2 fvco 10312.5} 171.875000 {refclk 171.875000 m 30 n 1 lpfd 2 lpd 2 fvco 10312.5} 166.330645 {refclk 166.330645 m 31 n 1 lpfd 2 lpd 2 fvco 10312.5} 332.661290 {refclk 332.661290 m 31 n 2 lpfd 2 lpd 2 fvco 10312.5} 665.322581 {refclk 665.322581 m 31 n 4 lpfd 2 lpd 2 fvco 10312.5} 161.132812 {refclk 161.132812 m 32 n 1 lpfd 2 lpd 2 fvco 10312.5} 156.250000 {refclk 156.250000 m 33 n 1 lpfd 2 lpd 2 fvco 10312.5} 312.500000 {refclk 312.500000 m 33 n 2 lpfd 2 lpd 2 fvco 10312.5} 625.000000 {refclk 625.000000 m 33 n 4 lpfd 2 lpd 2 fvco 10312.5} 151.654412 {refclk 151.654412 m 34 n 1 lpfd 2 lpd 2 fvco 10312.5} 147.321429 {refclk 147.321429 m 35 n 1 lpfd 2 lpd 2 fvco 10312.5} 294.642857 {refclk 294.642857 m 35 n 2 lpfd 2 lpd 2 fvco 10312.5} 589.285714 {refclk 589.285714 m 35 n 4 lpfd 2 lpd 2 fvco 10312.5} 143.229167 {refclk 143.229167 m 36 n 1 lpfd 2 lpd 2 fvco 10312.5} 139.358108 {refclk 139.358108 m 37 n 1 lpfd 2 lpd 2 fvco 10312.5} 278.716216 {refclk 278.716216 m 37 n 2 lpfd 2 lpd 2 fvco 10312.5} 557.432432 {refclk 557.432432 m 37 n 4 lpfd 2 lpd 2 fvco 10312.5} 135.690789 {refclk 135.690789 m 38 n 1 lpfd 2 lpd 2 fvco 10312.5} 132.211538 {refclk 132.211538 m 39 n 1 lpfd 2 lpd 2 fvco 10312.5} 264.423077 {refclk 264.423077 m 39 n 2 lpfd 2 lpd 2 fvco 10312.5} 528.846154 {refclk 528.846154 m 39 n 4 lpfd 2 lpd 2 fvco 10312.5} 128.906250 {refclk 128.906250 m 40 n 1 lpfd 2 lpd 2 fvco 10312.5} 125.762195 {refclk 125.762195 m 41 n 1 lpfd 2 lpd 2 fvco 10312.5} 251.524390 {refclk 251.524390 m 41 n 2 lpfd 2 lpd 2 fvco 10312.5} 503.048780 {refclk 503.048780 m 41 n 4 lpfd 2 lpd 2 fvco 10312.5} 122.767857 {refclk 122.767857 m 42 n 1 lpfd 2 lpd 2 fvco 10312.5} 119.912791 {refclk 119.912791 m 43 n 1 lpfd 2 lpd 2 fvco 10312.5} 239.825581 {refclk 239.825581 m 43 n 2 lpfd 2 lpd 2 fvco 10312.5} 479.651163 {refclk 479.651163 m 43 n 4 lpfd 2 lpd 2 fvco 10312.5} 117.187500 {refclk 117.187500 m 44 n 1 lpfd 2 lpd 2 fvco 10312.5} 114.583333 {refclk 114.583333 m 45 n 1 lpfd 2 lpd 2 fvco 10312.5} 229.166667 {refclk 229.166667 m 45 n 2 lpfd 2 lpd 2 fvco 10312.5} 458.333333 {refclk 458.333333 m 45 n 4 lpfd 2 lpd 2 fvco 10312.5} 112.092391 {refclk 112.092391 m 46 n 1 lpfd 2 lpd 2 fvco 10312.5} 109.707447 {refclk 109.707447 m 47 n 1 lpfd 2 lpd 2 fvco 10312.5} 219.414894 {refclk 219.414894 m 47 n 2 lpfd 2 lpd 2 fvco 10312.5} 438.829787 {refclk 438.829787 m 47 n 4 lpfd 2 lpd 2 fvco 10312.5} 107.421875 {refclk 107.421875 m 48 n 1 lpfd 2 lpd 2 fvco 10312.5} 105.229592 {refclk 105.229592 m 49 n 1 lpfd 2 lpd 2 fvco 10312.5} 210.459184 {refclk 210.459184 m 49 n 2 lpfd 2 lpd 2 fvco 10312.5} 420.918367 {refclk 420.918367 m 49 n 4 lpfd 2 lpd 2 fvco 10312.5} 103.125000 {refclk 103.125000 m 50 n 1 lpfd 2 lpd 2 fvco 10312.5} 101.102941 {refclk 101.102941 m 51 n 1 lpfd 2 lpd 2 fvco 10312.5} 202.205882 {refclk 202.205882 m 51 n 2 lpfd 2 lpd 2 fvco 10312.5} 404.411765 {refclk 404.411765 m 51 n 4 lpfd 2 lpd 2 fvco 10312.5} 99.158654 {refclk 99.158654 m 52 n 1 lpfd 2 lpd 2 fvco 10312.5} 97.287736 {refclk 97.287736 m 53 n 1 lpfd 2 lpd 2 fvco 10312.5} 194.575472 {refclk 194.575472 m 53 n 2 lpfd 2 lpd 2 fvco 10312.5} 389.150943 {refclk 389.150943 m 53 n 4 lpfd 2 lpd 2 fvco 10312.5} 778.301887 {refclk 778.301887 m 53 n 8 lpfd 2 lpd 2 fvco 10312.5} 95.486111 {refclk 95.486111 m 54 n 1 lpfd 2 lpd 2 fvco 10312.5} 93.750000 {refclk 93.750000 m 55 n 1 lpfd 2 lpd 2 fvco 10312.5} 187.500000 {refclk 187.500000 m 55 n 2 lpfd 2 lpd 2 fvco 10312.5} 375.000000 {refclk 375.000000 m 55 n 4 lpfd 2 lpd 2 fvco 10312.5} 750.000000 {refclk 750.000000 m 55 n 8 lpfd 2 lpd 2 fvco 10312.5} 92.075893 {refclk 92.075893 m 56 n 1 lpfd 2 lpd 2 fvco 10312.5} 90.460526 {refclk 90.460526 m 57 n 1 lpfd 2 lpd 2 fvco 10312.5} 180.921053 {refclk 180.921053 m 57 n 2 lpfd 2 lpd 2 fvco 10312.5} 361.842105 {refclk 361.842105 m 57 n 4 lpfd 2 lpd 2 fvco 10312.5} 723.684211 {refclk 723.684211 m 57 n 8 lpfd 2 lpd 2 fvco 10312.5} 88.900862 {refclk 88.900862 m 58 n 1 lpfd 2 lpd 2 fvco 10312.5} 87.394068 {refclk 87.394068 m 59 n 1 lpfd 2 lpd 2 fvco 10312.5} 174.788136 {refclk 174.788136 m 59 n 2 lpfd 2 lpd 2 fvco 10312.5} 349.576271 {refclk 349.576271 m 59 n 4 lpfd 2 lpd 2 fvco 10312.5} 699.152542 {refclk 699.152542 m 59 n 8 lpfd 2 lpd 2 fvco 10312.5} 85.937500 {refclk 85.937500 m 60 n 1 lpfd 2 lpd 2 fvco 10312.5} 84.528689 {refclk 84.528689 m 61 n 1 lpfd 2 lpd 2 fvco 10312.5} 169.057377 {refclk 169.057377 m 61 n 2 lpfd 2 lpd 2 fvco 10312.5} 338.114754 {refclk 338.114754 m 61 n 4 lpfd 2 lpd 2 fvco 10312.5} 676.229508 {refclk 676.229508 m 61 n 8 lpfd 2 lpd 2 fvco 10312.5} 83.165323 {refclk 83.165323 m 62 n 1 lpfd 2 lpd 2 fvco 10312.5} 81.845238 {refclk 81.845238 m 63 n 1 lpfd 2 lpd 2 fvco 10312.5} 163.690476 {refclk 163.690476 m 63 n 2 lpfd 2 lpd 2 fvco 10312.5} 327.380952 {refclk 327.380952 m 63 n 4 lpfd 2 lpd 2 fvco 10312.5} 654.761905 {refclk 654.761905 m 63 n 8 lpfd 2 lpd 2 fvco 10312.5} 80.566406 {refclk 80.566406 m 64 n 1 lpfd 2 lpd 2 fvco 10312.5} 79.326923 {refclk 79.326923 m 65 n 1 lpfd 2 lpd 2 fvco 10312.5} 158.653846 {refclk 158.653846 m 65 n 2 lpfd 2 lpd 2 fvco 10312.5} 317.307692 {refclk 317.307692 m 65 n 4 lpfd 2 lpd 2 fvco 10312.5} 634.615385 {refclk 634.615385 m 65 n 8 lpfd 2 lpd 2 fvco 10312.5} 78.125000 {refclk 78.125000 m 66 n 1 lpfd 2 lpd 2 fvco 10312.5} 76.958955 {refclk 76.958955 m 67 n 1 lpfd 2 lpd 2 fvco 10312.5} 153.917910 {refclk 153.917910 m 67 n 2 lpfd 2 lpd 2 fvco 10312.5} 307.835821 {refclk 307.835821 m 67 n 4 lpfd 2 lpd 2 fvco 10312.5} 615.671642 {refclk 615.671642 m 67 n 8 lpfd 2 lpd 2 fvco 10312.5} 75.827206 {refclk 75.827206 m 68 n 1 lpfd 2 lpd 2 fvco 10312.5} 74.728261 {refclk 74.728261 m 69 n 1 lpfd 2 lpd 2 fvco 10312.5} 149.456522 {refclk 149.456522 m 69 n 2 lpfd 2 lpd 2 fvco 10312.5} 298.913043 {refclk 298.913043 m 69 n 4 lpfd 2 lpd 2 fvco 10312.5} 597.826087 {refclk 597.826087 m 69 n 8 lpfd 2 lpd 2 fvco 10312.5} 73.660714 {refclk 73.660714 m 70 n 1 lpfd 2 lpd 2 fvco 10312.5} 72.623239 {refclk 72.623239 m 71 n 1 lpfd 2 lpd 2 fvco 10312.5} 145.246479 {refclk 145.246479 m 71 n 2 lpfd 2 lpd 2 fvco 10312.5} 290.492958 {refclk 290.492958 m 71 n 4 lpfd 2 lpd 2 fvco 10312.5} 580.985915 {refclk 580.985915 m 71 n 8 lpfd 2 lpd 2 fvco 10312.5} 71.614583 {refclk 71.614583 m 72 n 1 lpfd 2 lpd 2 fvco 10312.5} 70.633562 {refclk 70.633562 m 73 n 1 lpfd 2 lpd 2 fvco 10312.5} 141.267123 {refclk 141.267123 m 73 n 2 lpfd 2 lpd 2 fvco 10312.5} 282.534247 {refclk 282.534247 m 73 n 4 lpfd 2 lpd 2 fvco 10312.5} 565.068493 {refclk 565.068493 m 73 n 8 lpfd 2 lpd 2 fvco 10312.5} 69.679054 {refclk 69.679054 m 74 n 1 lpfd 2 lpd 2 fvco 10312.5} 68.750000 {refclk 68.750000 m 75 n 1 lpfd 2 lpd 2 fvco 10312.5} 137.500000 {refclk 137.500000 m 75 n 2 lpfd 2 lpd 2 fvco 10312.5} 275.000000 {refclk 275.000000 m 75 n 4 lpfd 2 lpd 2 fvco 10312.5} 550.000000 {refclk 550.000000 m 75 n 8 lpfd 2 lpd 2 fvco 10312.5} 67.845395 {refclk 67.845395 m 76 n 1 lpfd 2 lpd 2 fvco 10312.5} 66.964286 {refclk 66.964286 m 77 n 1 lpfd 2 lpd 2 fvco 10312.5} 133.928571 {refclk 133.928571 m 77 n 2 lpfd 2 lpd 2 fvco 10312.5} 267.857143 {refclk 267.857143 m 77 n 4 lpfd 2 lpd 2 fvco 10312.5} 535.714286 {refclk 535.714286 m 77 n 8 lpfd 2 lpd 2 fvco 10312.5} 66.105769 {refclk 66.105769 m 78 n 1 lpfd 2 lpd 2 fvco 10312.5} 65.268987 {refclk 65.268987 m 79 n 1 lpfd 2 lpd 2 fvco 10312.5} 130.537975 {refclk 130.537975 m 79 n 2 lpfd 2 lpd 2 fvco 10312.5} 261.075949 {refclk 261.075949 m 79 n 4 lpfd 2 lpd 2 fvco 10312.5} 522.151899 {refclk 522.151899 m 79 n 8 lpfd 2 lpd 2 fvco 10312.5} 64.453125 {refclk 64.453125 m 80 n 1 lpfd 2 lpd 2 fvco 10312.5} 63.657407 {refclk 63.657407 m 81 n 1 lpfd 2 lpd 2 fvco 10312.5} 127.314815 {refclk 127.314815 m 81 n 2 lpfd 2 lpd 2 fvco 10312.5} 254.629630 {refclk 254.629630 m 81 n 4 lpfd 2 lpd 2 fvco 10312.5} 509.259259 {refclk 509.259259 m 81 n 8 lpfd 2 lpd 2 fvco 10312.5} 62.881098 {refclk 62.881098 m 82 n 1 lpfd 2 lpd 2 fvco 10312.5} 62.123494 {refclk 62.123494 m 83 n 1 lpfd 2 lpd 2 fvco 10312.5} 124.246988 {refclk 124.246988 m 83 n 2 lpfd 2 lpd 2 fvco 10312.5} 248.493976 {refclk 248.493976 m 83 n 4 lpfd 2 lpd 2 fvco 10312.5} 496.987952 {refclk 496.987952 m 83 n 8 lpfd 2 lpd 2 fvco 10312.5} 61.383929 {refclk 61.383929 m 84 n 1 lpfd 2 lpd 2 fvco 10312.5} 60.661765 {refclk 60.661765 m 85 n 1 lpfd 2 lpd 2 fvco 10312.5} 121.323529 {refclk 121.323529 m 85 n 2 lpfd 2 lpd 2 fvco 10312.5} 242.647059 {refclk 242.647059 m 85 n 4 lpfd 2 lpd 2 fvco 10312.5} 485.294118 {refclk 485.294118 m 85 n 8 lpfd 2 lpd 2 fvco 10312.5} 59.956395 {refclk 59.956395 m 86 n 1 lpfd 2 lpd 2 fvco 10312.5} 59.267241 {refclk 59.267241 m 87 n 1 lpfd 2 lpd 2 fvco 10312.5} 118.534483 {refclk 118.534483 m 87 n 2 lpfd 2 lpd 2 fvco 10312.5} 237.068966 {refclk 237.068966 m 87 n 4 lpfd 2 lpd 2 fvco 10312.5} 474.137931 {refclk 474.137931 m 87 n 8 lpfd 2 lpd 2 fvco 10312.5} 58.593750 {refclk 58.593750 m 88 n 1 lpfd 2 lpd 2 fvco 10312.5} 57.935393 {refclk 57.935393 m 89 n 1 lpfd 2 lpd 2 fvco 10312.5} 115.870787 {refclk 115.870787 m 89 n 2 lpfd 2 lpd 2 fvco 10312.5} 231.741573 {refclk 231.741573 m 89 n 4 lpfd 2 lpd 2 fvco 10312.5} 463.483146 {refclk 463.483146 m 89 n 8 lpfd 2 lpd 2 fvco 10312.5} 57.291667 {refclk 57.291667 m 90 n 1 lpfd 2 lpd 2 fvco 10312.5} 56.662088 {refclk 56.662088 m 91 n 1 lpfd 2 lpd 2 fvco 10312.5} 113.324176 {refclk 113.324176 m 91 n 2 lpfd 2 lpd 2 fvco 10312.5} 226.648352 {refclk 226.648352 m 91 n 4 lpfd 2 lpd 2 fvco 10312.5} 453.296703 {refclk 453.296703 m 91 n 8 lpfd 2 lpd 2 fvco 10312.5} 56.046196 {refclk 56.046196 m 92 n 1 lpfd 2 lpd 2 fvco 10312.5} 55.443548 {refclk 55.443548 m 93 n 1 lpfd 2 lpd 2 fvco 10312.5} 110.887097 {refclk 110.887097 m 93 n 2 lpfd 2 lpd 2 fvco 10312.5} 221.774194 {refclk 221.774194 m 93 n 4 lpfd 2 lpd 2 fvco 10312.5} 443.548387 {refclk 443.548387 m 93 n 8 lpfd 2 lpd 2 fvco 10312.5} 54.853723 {refclk 54.853723 m 94 n 1 lpfd 2 lpd 2 fvco 10312.5} 54.276316 {refclk 54.276316 m 95 n 1 lpfd 2 lpd 2 fvco 10312.5} 108.552632 {refclk 108.552632 m 95 n 2 lpfd 2 lpd 2 fvco 10312.5} 217.105263 {refclk 217.105263 m 95 n 4 lpfd 2 lpd 2 fvco 10312.5} 434.210526 {refclk 434.210526 m 95 n 8 lpfd 2 lpd 2 fvco 10312.5} 53.710938 {refclk 53.710938 m 96 n 1 lpfd 2 lpd 2 fvco 10312.5} 53.157216 {refclk 53.157216 m 97 n 1 lpfd 2 lpd 2 fvco 10312.5} 106.314433 {refclk 106.314433 m 97 n 2 lpfd 2 lpd 2 fvco 10312.5} 212.628866 {refclk 212.628866 m 97 n 4 lpfd 2 lpd 2 fvco 10312.5} 425.257732 {refclk 425.257732 m 97 n 8 lpfd 2 lpd 2 fvco 10312.5} 52.614796 {refclk 52.614796 m 98 n 1 lpfd 2 lpd 2 fvco 10312.5} 52.083333 {refclk 52.083333 m 99 n 1 lpfd 2 lpd 2 fvco 10312.5} 104.166667 {refclk 104.166667 m 99 n 2 lpfd 2 lpd 2 fvco 10312.5} 208.333333 {refclk 208.333333 m 99 n 4 lpfd 2 lpd 2 fvco 10312.5} 416.666667 {refclk 416.666667 m 99 n 8 lpfd 2 lpd 2 fvco 10312.5} 51.562500 {refclk 51.562500 m 100 n 1 lpfd 2 lpd 2 fvco 10312.5} 51.051980 {refclk 51.051980 m 101 n 1 lpfd 2 lpd 2 fvco 10312.5} 102.103960 {refclk 102.103960 m 101 n 2 lpfd 2 lpd 2 fvco 10312.5} 204.207921 {refclk 204.207921 m 101 n 4 lpfd 2 lpd 2 fvco 10312.5} 408.415842 {refclk 408.415842 m 101 n 8 lpfd 2 lpd 2 fvco 10312.5} 50.551471 {refclk 50.551471 m 102 n 1 lpfd 2 lpd 2 fvco 10312.5} 50.060680 {refclk 50.060680 m 103 n 1 lpfd 2 lpd 2 fvco 10312.5} 100.121359 {refclk 100.121359 m 103 n 2 lpfd 2 lpd 2 fvco 10312.5} 200.242718 {refclk 200.242718 m 103 n 4 lpfd 2 lpd 2 fvco 10312.5} 400.485437 {refclk 400.485437 m 103 n 8 lpfd 2 lpd 2 fvco 10312.5} 49.579327 {refclk 49.579327 m 104 n 1 lpfd 2 lpd 2 fvco 10312.5} 49.107143 {refclk 49.107143 m 105 n 1 lpfd 2 lpd 2 fvco 10312.5} 98.214286 {refclk 98.214286 m 105 n 2 lpfd 2 lpd 2 fvco 10312.5} 196.428571 {refclk 196.428571 m 105 n 4 lpfd 2 lpd 2 fvco 10312.5} 392.857143 {refclk 392.857143 m 105 n 8 lpfd 2 lpd 2 fvco 10312.5} 48.643868 {refclk 48.643868 m 106 n 1 lpfd 2 lpd 2 fvco 10312.5} 48.189252 {refclk 48.189252 m 107 n 1 lpfd 2 lpd 2 fvco 10312.5} 96.378505 {refclk 96.378505 m 107 n 2 lpfd 2 lpd 2 fvco 10312.5} 192.757009 {refclk 192.757009 m 107 n 4 lpfd 2 lpd 2 fvco 10312.5} 385.514019 {refclk 385.514019 m 107 n 8 lpfd 2 lpd 2 fvco 10312.5} 47.743056 {refclk 47.743056 m 108 n 1 lpfd 2 lpd 2 fvco 10312.5} 47.305046 {refclk 47.305046 m 109 n 1 lpfd 2 lpd 2 fvco 10312.5} 94.610092 {refclk 94.610092 m 109 n 2 lpfd 2 lpd 2 fvco 10312.5} 189.220183 {refclk 189.220183 m 109 n 4 lpfd 2 lpd 2 fvco 10312.5} 378.440367 {refclk 378.440367 m 109 n 8 lpfd 2 lpd 2 fvco 10312.5} 46.875000 {refclk 46.875000 m 110 n 1 lpfd 2 lpd 2 fvco 10312.5} 46.452703 {refclk 46.452703 m 111 n 1 lpfd 2 lpd 2 fvco 10312.5} 92.905405 {refclk 92.905405 m 111 n 2 lpfd 2 lpd 2 fvco 10312.5} 185.810811 {refclk 185.810811 m 111 n 4 lpfd 2 lpd 2 fvco 10312.5} 371.621622 {refclk 371.621622 m 111 n 8 lpfd 2 lpd 2 fvco 10312.5} 46.037946 {refclk 46.037946 m 112 n 1 lpfd 2 lpd 2 fvco 10312.5} 45.630531 {refclk 45.630531 m 113 n 1 lpfd 2 lpd 2 fvco 10312.5} 91.261062 {refclk 91.261062 m 113 n 2 lpfd 2 lpd 2 fvco 10312.5} 182.522124 {refclk 182.522124 m 113 n 4 lpfd 2 lpd 2 fvco 10312.5} 365.044248 {refclk 365.044248 m 113 n 8 lpfd 2 lpd 2 fvco 10312.5} 45.230263 {refclk 45.230263 m 114 n 1 lpfd 2 lpd 2 fvco 10312.5} 44.836957 {refclk 44.836957 m 115 n 1 lpfd 2 lpd 2 fvco 10312.5} 89.673913 {refclk 89.673913 m 115 n 2 lpfd 2 lpd 2 fvco 10312.5} 179.347826 {refclk 179.347826 m 115 n 4 lpfd 2 lpd 2 fvco 10312.5} 358.695652 {refclk 358.695652 m 115 n 8 lpfd 2 lpd 2 fvco 10312.5} 44.450431 {refclk 44.450431 m 116 n 1 lpfd 2 lpd 2 fvco 10312.5} 44.070513 {refclk 44.070513 m 117 n 1 lpfd 2 lpd 2 fvco 10312.5} 88.141026 {refclk 88.141026 m 117 n 2 lpfd 2 lpd 2 fvco 10312.5} 176.282051 {refclk 176.282051 m 117 n 4 lpfd 2 lpd 2 fvco 10312.5} 352.564103 {refclk 352.564103 m 117 n 8 lpfd 2 lpd 2 fvco 10312.5} 43.697034 {refclk 43.697034 m 118 n 1 lpfd 2 lpd 2 fvco 10312.5} 43.329832 {refclk 43.329832 m 119 n 1 lpfd 2 lpd 2 fvco 10312.5} 86.659664 {refclk 86.659664 m 119 n 2 lpfd 2 lpd 2 fvco 10312.5} 173.319328 {refclk 173.319328 m 119 n 4 lpfd 2 lpd 2 fvco 10312.5} 346.638655 {refclk 346.638655 m 119 n 8 lpfd 2 lpd 2 fvco 10312.5} 42.968750 {refclk 42.968750 m 120 n 1 lpfd 2 lpd 2 fvco 10312.5} 42.613636 {refclk 42.613636 m 121 n 1 lpfd 2 lpd 2 fvco 10312.5} 85.227273 {refclk 85.227273 m 121 n 2 lpfd 2 lpd 2 fvco 10312.5} 170.454545 {refclk 170.454545 m 121 n 4 lpfd 2 lpd 2 fvco 10312.5} 340.909091 {refclk 340.909091 m 121 n 8 lpfd 2 lpd 2 fvco 10312.5} 42.264344 {refclk 42.264344 m 122 n 1 lpfd 2 lpd 2 fvco 10312.5} 41.920732 {refclk 41.920732 m 123 n 1 lpfd 2 lpd 2 fvco 10312.5} 83.841463 {refclk 83.841463 m 123 n 2 lpfd 2 lpd 2 fvco 10312.5} 167.682927 {refclk 167.682927 m 123 n 4 lpfd 2 lpd 2 fvco 10312.5} 335.365854 {refclk 335.365854 m 123 n 8 lpfd 2 lpd 2 fvco 10312.5} 41.582661 {refclk 41.582661 m 124 n 1 lpfd 2 lpd 2 fvco 10312.5} 41.250000 {refclk 41.250000 m 125 n 1 lpfd 2 lpd 2 fvco 10312.5} 82.500000 {refclk 82.500000 m 125 n 2 lpfd 2 lpd 2 fvco 10312.5} 165.000000 {refclk 165.000000 m 125 n 4 lpfd 2 lpd 2 fvco 10312.5} 330.000000 {refclk 330.000000 m 125 n 8 lpfd 2 lpd 2 fvco 10312.5} 40.922619 {refclk 40.922619 m 126 n 1 lpfd 2 lpd 2 fvco 10312.5} 40.600394 {refclk 40.600394 m 127 n 1 lpfd 2 lpd 2 fvco 10312.5} 81.200787 {refclk 81.200787 m 127 n 2 lpfd 2 lpd 2 fvco 10312.5} 162.401575 {refclk 162.401575 m 127 n 4 lpfd 2 lpd 2 fvco 10312.5} 324.803150 {refclk 324.803150 m 127 n 8 lpfd 2 lpd 2 fvco 10312.5} allowed_ranges {40.600394 40.922619 41.250000 41.582661 41.920732 42.264344 42.613636 42.968750 43.329832 43.697034 44.070513 44.450431 44.836957 45.230263 45.630531 46.037946 46.452703 46.875000 47.305046 47.743056 48.189252 48.643868 49.107143 49.579327 50.060680 50.551471 51.051980 51.562500 52.083333 52.614796 53.157216 53.710938 54.276316 54.853723 55.443548 56.046196 56.662088 57.291667 57.935393 58.593750 59.267241 59.956395 60.661765 61.383929 62.123494 62.881098 63.657407 64.453125 65.268987 66.105769 66.964286 67.845395 68.750000 69.679054 70.633562 71.614583 72.623239 73.660714 74.728261 75.827206 76.958955 78.125000 79.326923 80.566406 81.200787 81.845238 82.500000 83.165323 83.841463 84.528689 85.227273 85.937500 86.659664 87.394068 88.141026 88.900862 89.673913 90.460526 91.261062 92.075893 92.905405 93.750000 94.610092 95.486111 96.378505 97.287736 98.214286 99.158654 100.121359 101.102941 102.103960 103.125000 104.166667 105.229592 106.314433 107.421875 108.552632 109.707447 110.887097 112.092391 113.324176 114.583333 115.870787 117.187500 118.534483 119.912791 121.323529 122.767857 124.246988 125.762195 127.314815 128.906250 130.537975 132.211538 133.928571 135.690789 137.500000 139.358108 141.267123 143.229167 145.246479 147.321429 149.456522 151.654412 153.917910 156.250000 158.653846 161.132812 162.401575 163.690476 165.000000 166.330645 167.682927 169.057377 170.454545 171.875000 173.319328 174.788136 176.282051 177.801724 179.347826 180.921053 182.522124 184.151786 185.810811 187.500000 189.220183 190.972222 192.757009 194.575472 196.428571 198.317308 200.242718 202.205882 204.207921 206.250000 208.333333 210.459184 212.628866 214.843750 217.105263 219.414894 221.774194 224.184783 226.648352 229.166667 231.741573 234.375000 237.068966 239.825581 242.647059 245.535714 248.493976 251.524390 254.629630 257.812500 261.075949 264.423077 267.857143 271.381579 275.000000 278.716216 282.534247 286.458333 290.492958 294.642857 298.913043 303.308824 307.835821 312.500000 317.307692 322.265625 324.803150 327.380952 330.000000 332.661290 335.365854 338.114754 340.909091 343.750000 346.638655 349.576271 352.564103 355.603448 358.695652 361.842105 365.044248 368.303571 371.621622 375.000000 378.440367 381.944444 385.514019 389.150943 392.857143 396.634615 400.485437 404.411765 408.415842 412.500000 416.666667 420.918367 425.257732 429.687500 434.210526 438.829787 443.548387 448.369565 453.296703 458.333333 463.483146 468.750000 474.137931 479.651163 485.294118 491.071429 496.987952 503.048780 509.259259 515.625000 522.151899 528.846154 535.714286 542.763158 550.000000 557.432432 565.068493 572.916667 580.985915 589.285714 597.826087 606.617647 615.671642 625.000000 634.615385 644.531250 654.761905 665.322581 676.229508 687.500000 699.152542 711.206897 723.684211 736.607143 750.000000 763.888889 778.301887 793.269231} l_pll_settings_key l_pll_settings_key 644.531250 enable_std enable_std 0 l_enable_std_pipe l_enable_std_pipe 0 l_enable_tx_std l_enable_tx_std 0 l_enable_rx_std l_enable_rx_std 0 l_std_tx_word_count l_std_tx_word_count 1 l_std_tx_word_width l_std_tx_word_width 10 l_std_tx_field_width l_std_tx_field_width 11 l_std_rx_word_count l_std_rx_word_count 1 l_std_rx_word_width l_std_rx_word_width 10 l_std_rx_field_width l_std_rx_field_width 16 l_std_tx_pld_pcs_width l_std_tx_pld_pcs_width 10 l_std_rx_pld_pcs_width l_std_rx_pld_pcs_width 10 enable_enh enable_enh 1 l_enable_tx_enh l_enable_tx_enh 1 l_enable_rx_enh l_enable_rx_enh 1 enable_pcs_dir enable_pcs_dir 0 l_enable_tx_pcs_dir l_enable_tx_pcs_dir 0 l_enable_rx_pcs_dir l_enable_rx_pcs_dir 0 l_rcfg_ifaces l_rcfg_ifaces 4 l_rcfg_addr_bits l_rcfg_addr_bits 11 ovrd_tx_dv_mode Enable TX Data Valid Gen manual setting 0 usr_tx_dv_mode Generate TX Data Valid by Core AIB FIFO enable ovrd_rx_dv_mode Enable RX Data Valid Rcv manual setting 0 usr_rx_dv_mode Consume RX Data Valid by Core AIB FIFO enable rcfg_shared Share reconfiguration interface 0 rcfg_use_clk_reset_only Use AVMM clock and reset ports only 0 adme_prot_mode adme_prot_mode basic_enh adme_pma_mode adme_pma_mode basic adme_tx_power_mode adme_tx_power_mode mid_power adme_data_rate adme_data_rate 10312500000 adme_enable_bg_cal adme_enable_bg_cal 0 set_embedded_debug_enable Enable embedded debug 0 set_prbs_soft_logic_enable Enable prbs soft accumulators 0 set_odi_soft_logic_enable Enable odi acceleration logic 0 dbg_prbs_soft_logic_enable dbg_prbs_soft_logic_enable 0 dbg_odi_soft_logic_enable dbg_odi_soft_logic_enable 0 l_rcfg_datapath_message l_rcfg_datapath_message 0 enable_rcfg_tx_digitalreset_release_ctrl Enable rcfg_tx_digitalreset_release_ctrl port 0 cannot_gen_exdesign_msg cannot_gen_exdesign_msg Design example cannot be generated for the current configuration. Please check under Design Example tab and system message below for more detailed information. cannot_gen_exdesign_gen_msg cannot_gen_exdesign_gen_msg For multi channel configurations, a design example cannot be generated unless "Provide separate interface for each channel" is selected. cannot_gen_exdesign_prot_msg cannot_gen_exdesign_prot_msg can_gen_exdesign_basic_std can_gen_exdesign_basic_std 1 can_gen_exdesign_basic_enh can_gen_exdesign_basic_enh 1 can_gen_exdesign_pcs_direct can_gen_exdesign_pcs_direct 1 can_gen_exdesign_pcie_pipe can_gen_exdesign_pcie_pipe 1 can_gen_exdesign_cpri_auto can_gen_exdesign_cpri_auto 1 suppress_design_example_messages suppress_design_example_messages 0 enable_workaround_rules Enable workaround rules 0 tx_pll_type Tx PLL type ATX design_example_tx_pll_kind Tx PLL kind altera_xcvr_atx_pll_s10_htile tx_pll_refclk Tx PLL reference clock frequency 644.53125 use_tx_clkout2 Use tx_clkout2 as source for tx_coreclkin 0 use_rx_clkout2 Use rx_clkout2 as source for rx_coreclkin 0 enable_de_hardware_debug Enable soft register map for System Console 0 lcl_enable_fast_sim_option lcl_enable_fast_sim_option 0 enable_fast_sim Enable fast simulations 0 enable_mac_total_control Enable MAC total control of PHY settings 0 enable_insert_eios_err Enable PCIe EIOS error insertion 0 tile_type_suffix Xcvr Tile Type Suffix design_example_filename Design example filename top anlg_voltage VCCR_GXB and VCCT_GXB supply voltage for the Transceiver 1_0V anlg_link Tranceiver Link Type sr enable_ports_adaptation Enable adaptation control ports 0 qsf_assignments_enable Provide sample QSF assignments 0 qsf_assignments_list Sample QSF Assignments enable_backup_pma_adapt_modes enable_backup_pma_adapt_modes 0 tx_pma_analog_mode TX PMA analog mode rules user_custom rx_pma_analog_mode RX PMA analog mode rules user_custom tx_pma_optimal_settings Use default TX PMA analog settings 1 l_tx_pma_optimal_settings l_tx_pma_optimal_settings true l_tx_pma_optimal_atom_settings l_tx_pma_optimal_atom_settings true tx_pma_output_swing_ctrl Output Swing Level (VOD) 12 tx_pma_pre_emp_sign_pre_tap_1t Pre-Emphasis First Pre-Tap Polarity negative tx_pma_pre_emp_switching_ctrl_pre_tap_1t Pre-Emphasis First Pre-Tap Magnitude 0 tx_pma_pre_emp_sign_1st_post_tap Pre-Emphasis First Post-Tap Polarity negative tx_pma_pre_emp_switching_ctrl_1st_post_tap Pre-Emphasis First Post-Tap Magnitude 0 tx_output_swing_message tx_output_swing_message tx_pma_slew_rate_ctrl Slew Rate Control 0 tx_pma_term_sel On-Chip Termination r_r1 tx_pma_compensation_en High Speed Compensation enable rx_pma_optimal_settings Use default RX PMA analog settings 1 l_rx_pma_optimal_settings l_rx_pma_optimal_settings true l_adapt_mode_manual l_adapt_mode_manual 1 l_adapt_mode_dfe l_adapt_mode_dfe 0 rx_pma_adapt_mode RX adaptation mode manual rx_pma_term_sel RX On-chip Termination r_r2 rx_ctle_ac_gain CTLE AC Gain 0 rx_ctle_eq_gain CTLE EQ Gain 0 rx_vga_dc_gain VGA DC Gain 0 hssi_10g_rx_pcs_advanced_user_mode hssi_10g_rx_pcs_advanced_user_mode disable hssi_10g_rx_pcs_align_del hssi_10g_rx_pcs_align_del align_del_dis hssi_10g_rx_pcs_ber_bit_err_total_cnt hssi_10g_rx_pcs_ber_bit_err_total_cnt bit_err_total_cnt_10g hssi_10g_rx_pcs_ber_clken hssi_10g_rx_pcs_ber_clken ber_clk_dis hssi_10g_rx_pcs_ber_xus_timer_window hssi_10g_rx_pcs_ber_xus_timer_window 19530 hssi_10g_rx_pcs_bitslip_mode hssi_10g_rx_pcs_bitslip_mode bitslip_en hssi_10g_rx_pcs_blksync_bitslip_type hssi_10g_rx_pcs_blksync_bitslip_type bitslip_comb hssi_10g_rx_pcs_blksync_bitslip_wait_cnt hssi_10g_rx_pcs_blksync_bitslip_wait_cnt 1 hssi_10g_rx_pcs_blksync_bitslip_wait_type hssi_10g_rx_pcs_blksync_bitslip_wait_type bitslip_cnt hssi_10g_rx_pcs_blksync_bypass hssi_10g_rx_pcs_blksync_bypass blksync_bypass_en hssi_10g_rx_pcs_blksync_clken hssi_10g_rx_pcs_blksync_clken blksync_clk_en hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt enum_invalid_sh_cnt_10g hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock knum_sh_cnt_postlock_10g hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock knum_sh_cnt_prelock_10g hssi_10g_rx_pcs_blksync_pipeln hssi_10g_rx_pcs_blksync_pipeln blksync_pipeln_dis hssi_10g_rx_pcs_clr_errblk_cnt_en hssi_10g_rx_pcs_clr_errblk_cnt_en disable hssi_10g_rx_pcs_control_del hssi_10g_rx_pcs_control_del control_del_none hssi_10g_rx_pcs_crcchk_bypass hssi_10g_rx_pcs_crcchk_bypass crcchk_bypass_en hssi_10g_rx_pcs_crcchk_clken hssi_10g_rx_pcs_crcchk_clken crcchk_clk_dis hssi_10g_rx_pcs_crcchk_inv hssi_10g_rx_pcs_crcchk_inv crcchk_inv_en hssi_10g_rx_pcs_crcchk_pipeln hssi_10g_rx_pcs_crcchk_pipeln crcchk_pipeln_en hssi_10g_rx_pcs_crcflag_pipeln hssi_10g_rx_pcs_crcflag_pipeln crcflag_pipeln_en hssi_10g_rx_pcs_ctrl_bit_reverse hssi_10g_rx_pcs_ctrl_bit_reverse ctrl_bit_reverse_dis hssi_10g_rx_pcs_data_bit_reverse hssi_10g_rx_pcs_data_bit_reverse data_bit_reverse_dis hssi_10g_rx_pcs_dec64b66b_clken hssi_10g_rx_pcs_dec64b66b_clken dec64b66b_clk_dis hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass dec_64b66b_rxsm_bypass_en hssi_10g_rx_pcs_descrm_bypass hssi_10g_rx_pcs_descrm_bypass descrm_bypass_en hssi_10g_rx_pcs_descrm_clken hssi_10g_rx_pcs_descrm_clken descrm_clk_dis hssi_10g_rx_pcs_descrm_mode hssi_10g_rx_pcs_descrm_mode async hssi_10g_rx_pcs_descrm_pipeln hssi_10g_rx_pcs_descrm_pipeln enable hssi_10g_rx_pcs_dft_clk_out_sel hssi_10g_rx_pcs_dft_clk_out_sel rx_master_clk hssi_10g_rx_pcs_dis_signal_ok hssi_10g_rx_pcs_dis_signal_ok dis_signal_ok_dis hssi_10g_rx_pcs_dispchk_bypass hssi_10g_rx_pcs_dispchk_bypass dispchk_bypass_en hssi_10g_rx_pcs_empty_flag_type hssi_10g_rx_pcs_empty_flag_type empty_rd_side hssi_10g_rx_pcs_fast_path hssi_10g_rx_pcs_fast_path fast_path_en hssi_10g_rx_pcs_fec_clken hssi_10g_rx_pcs_fec_clken fec_clk_dis hssi_10g_rx_pcs_fec_enable hssi_10g_rx_pcs_fec_enable fec_dis hssi_10g_rx_pcs_fifo_double_read hssi_10g_rx_pcs_fifo_double_read fifo_double_read_dis hssi_10g_rx_pcs_fifo_stop_rd hssi_10g_rx_pcs_fifo_stop_rd n_rd_empty hssi_10g_rx_pcs_fifo_stop_wr hssi_10g_rx_pcs_fifo_stop_wr n_wr_full hssi_10g_rx_pcs_force_align hssi_10g_rx_pcs_force_align force_align_dis hssi_10g_rx_pcs_frmsync_bypass hssi_10g_rx_pcs_frmsync_bypass frmsync_bypass_en hssi_10g_rx_pcs_frmsync_clken hssi_10g_rx_pcs_frmsync_clken frmsync_clk_dis hssi_10g_rx_pcs_frmsync_enum_scrm hssi_10g_rx_pcs_frmsync_enum_scrm enum_scrm_default hssi_10g_rx_pcs_frmsync_enum_sync hssi_10g_rx_pcs_frmsync_enum_sync enum_sync_default hssi_10g_rx_pcs_frmsync_flag_type hssi_10g_rx_pcs_frmsync_flag_type location_only hssi_10g_rx_pcs_frmsync_knum_sync hssi_10g_rx_pcs_frmsync_knum_sync knum_sync_default hssi_10g_rx_pcs_frmsync_mfrm_length hssi_10g_rx_pcs_frmsync_mfrm_length 2048 hssi_10g_rx_pcs_frmsync_pipeln hssi_10g_rx_pcs_frmsync_pipeln frmsync_pipeln_en hssi_10g_rx_pcs_full_flag_type hssi_10g_rx_pcs_full_flag_type full_wr_side hssi_10g_rx_pcs_gb_rx_idwidth hssi_10g_rx_pcs_gb_rx_idwidth idwidth_64 hssi_10g_rx_pcs_gb_rx_odwidth hssi_10g_rx_pcs_gb_rx_odwidth odwidth_66 hssi_10g_rx_pcs_gbexp_clken hssi_10g_rx_pcs_gbexp_clken gbexp_clk_en hssi_10g_rx_pcs_low_latency_en hssi_10g_rx_pcs_low_latency_en disable hssi_10g_rx_pcs_lpbk_mode hssi_10g_rx_pcs_lpbk_mode lpbk_dis hssi_10g_rx_pcs_master_clk_sel hssi_10g_rx_pcs_master_clk_sel master_rx_pma_clk hssi_10g_rx_pcs_pempty_flag_type hssi_10g_rx_pcs_pempty_flag_type pempty_rd_side hssi_10g_rx_pcs_pfull_flag_type hssi_10g_rx_pcs_pfull_flag_type pfull_wr_side hssi_10g_rx_pcs_phcomp_rd_del hssi_10g_rx_pcs_phcomp_rd_del phcomp_rd_del2 hssi_10g_rx_pcs_pld_if_type hssi_10g_rx_pcs_pld_if_type reg hssi_10g_rx_pcs_prot_mode hssi_10g_rx_pcs_prot_mode basic_mode hssi_10g_rx_pcs_rand_clken hssi_10g_rx_pcs_rand_clken rand_clk_dis hssi_10g_rx_pcs_rd_clk_sel hssi_10g_rx_pcs_rd_clk_sel rd_rx_pma_clk hssi_10g_rx_pcs_rdfifo_clken hssi_10g_rx_pcs_rdfifo_clken rdfifo_clk_en hssi_10g_rx_pcs_rx_fifo_write_ctrl hssi_10g_rx_pcs_rx_fifo_write_ctrl blklock_stops hssi_10g_rx_pcs_rx_scrm_width hssi_10g_rx_pcs_rx_scrm_width bit64 hssi_10g_rx_pcs_rx_sh_location hssi_10g_rx_pcs_rx_sh_location msb hssi_10g_rx_pcs_rx_signal_ok_sel hssi_10g_rx_pcs_rx_signal_ok_sel synchronized_ver hssi_10g_rx_pcs_rx_sm_bypass hssi_10g_rx_pcs_rx_sm_bypass rx_sm_bypass_en hssi_10g_rx_pcs_rx_sm_hiber hssi_10g_rx_pcs_rx_sm_hiber rx_sm_hiber_en hssi_10g_rx_pcs_rx_sm_pipeln hssi_10g_rx_pcs_rx_sm_pipeln rx_sm_pipeln_en hssi_10g_rx_pcs_rx_testbus_sel hssi_10g_rx_pcs_rx_testbus_sel rx_fifo_testbus1 hssi_10g_rx_pcs_rx_true_b2b hssi_10g_rx_pcs_rx_true_b2b b2b hssi_10g_rx_pcs_rxfifo_empty hssi_10g_rx_pcs_rxfifo_empty empty_default hssi_10g_rx_pcs_rxfifo_full hssi_10g_rx_pcs_rxfifo_full full_default hssi_10g_rx_pcs_rxfifo_mode hssi_10g_rx_pcs_rxfifo_mode register_mode hssi_10g_rx_pcs_rxfifo_pempty hssi_10g_rx_pcs_rxfifo_pempty 2 hssi_10g_rx_pcs_rxfifo_pfull hssi_10g_rx_pcs_rxfifo_pfull 23 hssi_10g_rx_pcs_stretch_num_stages hssi_10g_rx_pcs_stretch_num_stages one_stage hssi_10g_rx_pcs_sup_mode hssi_10g_rx_pcs_sup_mode user_mode hssi_10g_rx_pcs_test_mode hssi_10g_rx_pcs_test_mode test_off hssi_10g_rx_pcs_wrfifo_clken hssi_10g_rx_pcs_wrfifo_clken wrfifo_clk_en hssi_10g_rx_pcs_silicon_rev hssi_10g_rx_pcs_silicon_rev 14nm5bcr2eb hssi_10g_rx_pcs_reconfig_settings hssi_10g_rx_pcs_reconfig_settings {} hssi_10g_tx_pcs_advanced_user_mode hssi_10g_tx_pcs_advanced_user_mode disable hssi_10g_tx_pcs_bitslip_en hssi_10g_tx_pcs_bitslip_en bitslip_dis hssi_10g_tx_pcs_bonding_dft_en hssi_10g_tx_pcs_bonding_dft_en dft_dis hssi_10g_tx_pcs_bonding_dft_val hssi_10g_tx_pcs_bonding_dft_val dft_0 hssi_10g_tx_pcs_comp_cnt hssi_10g_tx_pcs_comp_cnt 0 hssi_10g_tx_pcs_compin_sel hssi_10g_tx_pcs_compin_sel compin_master hssi_10g_tx_pcs_crcgen_bypass hssi_10g_tx_pcs_crcgen_bypass crcgen_bypass_en hssi_10g_tx_pcs_crcgen_clken hssi_10g_tx_pcs_crcgen_clken crcgen_clk_dis hssi_10g_tx_pcs_crcgen_err hssi_10g_tx_pcs_crcgen_err crcgen_err_dis hssi_10g_tx_pcs_crcgen_inv hssi_10g_tx_pcs_crcgen_inv crcgen_inv_en hssi_10g_tx_pcs_ctrl_bit_reverse hssi_10g_tx_pcs_ctrl_bit_reverse ctrl_bit_reverse_dis hssi_10g_tx_pcs_ctrl_plane_bonding hssi_10g_tx_pcs_ctrl_plane_bonding individual hssi_10g_tx_pcs_data_bit_reverse hssi_10g_tx_pcs_data_bit_reverse data_bit_reverse_dis hssi_10g_tx_pcs_dft_clk_out_sel hssi_10g_tx_pcs_dft_clk_out_sel tx_master_clk hssi_10g_tx_pcs_dispgen_bypass hssi_10g_tx_pcs_dispgen_bypass dispgen_bypass_en hssi_10g_tx_pcs_dispgen_clken hssi_10g_tx_pcs_dispgen_clken dispgen_clk_dis hssi_10g_tx_pcs_dispgen_err hssi_10g_tx_pcs_dispgen_err dispgen_err_dis hssi_10g_tx_pcs_dispgen_pipeln hssi_10g_tx_pcs_dispgen_pipeln dispgen_pipeln_dis hssi_10g_tx_pcs_distdwn_bypass_pipeln hssi_10g_tx_pcs_distdwn_bypass_pipeln distdwn_bypass_pipeln_dis hssi_10g_tx_pcs_distdwn_master hssi_10g_tx_pcs_distdwn_master distdwn_master_en hssi_10g_tx_pcs_distup_bypass_pipeln hssi_10g_tx_pcs_distup_bypass_pipeln distup_bypass_pipeln_dis hssi_10g_tx_pcs_distup_master hssi_10g_tx_pcs_distup_master distup_master_en hssi_10g_tx_pcs_dv_bond hssi_10g_tx_pcs_dv_bond dv_bond_dis hssi_10g_tx_pcs_empty_flag_type hssi_10g_tx_pcs_empty_flag_type empty_rd_side hssi_10g_tx_pcs_enc64b66b_txsm_clken hssi_10g_tx_pcs_enc64b66b_txsm_clken enc64b66b_txsm_clk_dis hssi_10g_tx_pcs_enc_64b66b_txsm_bypass hssi_10g_tx_pcs_enc_64b66b_txsm_bypass enc_64b66b_txsm_bypass_en hssi_10g_tx_pcs_fastpath hssi_10g_tx_pcs_fastpath fastpath_en hssi_10g_tx_pcs_fec_clken hssi_10g_tx_pcs_fec_clken fec_clk_dis hssi_10g_tx_pcs_fec_enable hssi_10g_tx_pcs_fec_enable fec_dis hssi_10g_tx_pcs_fifo_double_write hssi_10g_tx_pcs_fifo_double_write fifo_double_write_dis hssi_10g_tx_pcs_fifo_reg_fast hssi_10g_tx_pcs_fifo_reg_fast fifo_reg_fast_dis hssi_10g_tx_pcs_fifo_stop_rd hssi_10g_tx_pcs_fifo_stop_rd n_rd_empty hssi_10g_tx_pcs_fifo_stop_wr hssi_10g_tx_pcs_fifo_stop_wr n_wr_full hssi_10g_tx_pcs_frmgen_burst hssi_10g_tx_pcs_frmgen_burst frmgen_burst_dis hssi_10g_tx_pcs_frmgen_bypass hssi_10g_tx_pcs_frmgen_bypass frmgen_bypass_en hssi_10g_tx_pcs_frmgen_clken hssi_10g_tx_pcs_frmgen_clken frmgen_clk_dis hssi_10g_tx_pcs_frmgen_mfrm_length hssi_10g_tx_pcs_frmgen_mfrm_length 2048 hssi_10g_tx_pcs_frmgen_pipeln hssi_10g_tx_pcs_frmgen_pipeln frmgen_pipeln_en hssi_10g_tx_pcs_frmgen_pyld_ins hssi_10g_tx_pcs_frmgen_pyld_ins frmgen_pyld_ins_dis hssi_10g_tx_pcs_frmgen_wordslip hssi_10g_tx_pcs_frmgen_wordslip frmgen_wordslip_dis hssi_10g_tx_pcs_full_flag_type hssi_10g_tx_pcs_full_flag_type full_wr_side hssi_10g_tx_pcs_gb_pipeln_bypass hssi_10g_tx_pcs_gb_pipeln_bypass disable hssi_10g_tx_pcs_gb_tx_idwidth hssi_10g_tx_pcs_gb_tx_idwidth idwidth_66 hssi_10g_tx_pcs_gb_tx_odwidth hssi_10g_tx_pcs_gb_tx_odwidth odwidth_64 hssi_10g_tx_pcs_gbred_clken hssi_10g_tx_pcs_gbred_clken gbred_clk_en hssi_10g_tx_pcs_indv hssi_10g_tx_pcs_indv indv_en hssi_10g_tx_pcs_low_latency_en hssi_10g_tx_pcs_low_latency_en disable hssi_10g_tx_pcs_master_clk_sel hssi_10g_tx_pcs_master_clk_sel master_tx_pma_clk hssi_10g_tx_pcs_pempty_flag_type hssi_10g_tx_pcs_pempty_flag_type pempty_rd_side hssi_10g_tx_pcs_pfull_flag_type hssi_10g_tx_pcs_pfull_flag_type pfull_wr_side hssi_10g_tx_pcs_phcomp_rd_del hssi_10g_tx_pcs_phcomp_rd_del phcomp_rd_del2 hssi_10g_tx_pcs_pld_if_type hssi_10g_tx_pcs_pld_if_type reg hssi_10g_tx_pcs_prot_mode hssi_10g_tx_pcs_prot_mode basic_mode hssi_10g_tx_pcs_pseudo_random hssi_10g_tx_pcs_pseudo_random all_0 hssi_10g_tx_pcs_pseudo_seed_a hssi_10g_tx_pcs_pseudo_seed_a 288230376151711743 hssi_10g_tx_pcs_pseudo_seed_b hssi_10g_tx_pcs_pseudo_seed_b 288230376151711743 hssi_10g_tx_pcs_random_disp hssi_10g_tx_pcs_random_disp disable hssi_10g_tx_pcs_rdfifo_clken hssi_10g_tx_pcs_rdfifo_clken rdfifo_clk_en hssi_10g_tx_pcs_scrm_bypass hssi_10g_tx_pcs_scrm_bypass scrm_bypass_en hssi_10g_tx_pcs_scrm_clken hssi_10g_tx_pcs_scrm_clken scrm_clk_dis hssi_10g_tx_pcs_scrm_mode hssi_10g_tx_pcs_scrm_mode async hssi_10g_tx_pcs_scrm_pipeln hssi_10g_tx_pcs_scrm_pipeln enable hssi_10g_tx_pcs_sh_err hssi_10g_tx_pcs_sh_err sh_err_dis hssi_10g_tx_pcs_sop_mark hssi_10g_tx_pcs_sop_mark sop_mark_dis hssi_10g_tx_pcs_stretch_num_stages hssi_10g_tx_pcs_stretch_num_stages one_stage hssi_10g_tx_pcs_sup_mode hssi_10g_tx_pcs_sup_mode user_mode hssi_10g_tx_pcs_test_mode hssi_10g_tx_pcs_test_mode test_off hssi_10g_tx_pcs_tx_scrm_err hssi_10g_tx_pcs_tx_scrm_err scrm_err_dis hssi_10g_tx_pcs_tx_scrm_width hssi_10g_tx_pcs_tx_scrm_width bit64 hssi_10g_tx_pcs_tx_sh_location hssi_10g_tx_pcs_tx_sh_location msb hssi_10g_tx_pcs_tx_sm_bypass hssi_10g_tx_pcs_tx_sm_bypass tx_sm_bypass_en hssi_10g_tx_pcs_tx_sm_pipeln hssi_10g_tx_pcs_tx_sm_pipeln tx_sm_pipeln_en hssi_10g_tx_pcs_tx_testbus_sel hssi_10g_tx_pcs_tx_testbus_sel tx_fifo_testbus1 hssi_10g_tx_pcs_txfifo_empty hssi_10g_tx_pcs_txfifo_empty empty_default hssi_10g_tx_pcs_txfifo_full hssi_10g_tx_pcs_txfifo_full full_default hssi_10g_tx_pcs_txfifo_mode hssi_10g_tx_pcs_txfifo_mode register_mode hssi_10g_tx_pcs_txfifo_pempty hssi_10g_tx_pcs_txfifo_pempty 2 hssi_10g_tx_pcs_txfifo_pfull hssi_10g_tx_pcs_txfifo_pfull 11 hssi_10g_tx_pcs_wr_clk_sel hssi_10g_tx_pcs_wr_clk_sel wr_tx_pma_clk hssi_10g_tx_pcs_wrfifo_clken hssi_10g_tx_pcs_wrfifo_clken wrfifo_clk_en hssi_10g_tx_pcs_silicon_rev hssi_10g_tx_pcs_silicon_rev 14nm5bcr2eb hssi_10g_tx_pcs_reconfig_settings hssi_10g_tx_pcs_reconfig_settings {} hssi_8g_rx_pcs_auto_error_replacement hssi_8g_rx_pcs_auto_error_replacement dis_err_replace hssi_8g_rx_pcs_auto_speed_nego hssi_8g_rx_pcs_auto_speed_nego dis_asn hssi_8g_rx_pcs_bit_reversal hssi_8g_rx_pcs_bit_reversal dis_bit_reversal hssi_8g_rx_pcs_bonding_dft_en hssi_8g_rx_pcs_bonding_dft_en dft_dis hssi_8g_rx_pcs_bonding_dft_val hssi_8g_rx_pcs_bonding_dft_val dft_0 hssi_8g_rx_pcs_bypass_pipeline_reg hssi_8g_rx_pcs_bypass_pipeline_reg dis_bypass_pipeline hssi_8g_rx_pcs_byte_deserializer hssi_8g_rx_pcs_byte_deserializer dis_bds hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask dis_rxvalid_mask hssi_8g_rx_pcs_clkcmp_pattern_n hssi_8g_rx_pcs_clkcmp_pattern_n 0 hssi_8g_rx_pcs_clkcmp_pattern_p hssi_8g_rx_pcs_clkcmp_pattern_p 0 hssi_8g_rx_pcs_clock_gate_bds_dec_asn hssi_8g_rx_pcs_clock_gate_bds_dec_asn en_bds_dec_asn_clk_gating hssi_8g_rx_pcs_clock_gate_cdr_eidle hssi_8g_rx_pcs_clock_gate_cdr_eidle en_cdr_eidle_clk_gating hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk en_dw_pc_wrclk_gating hssi_8g_rx_pcs_clock_gate_dw_rm_rd hssi_8g_rx_pcs_clock_gate_dw_rm_rd en_dw_rm_rdclk_gating hssi_8g_rx_pcs_clock_gate_dw_rm_wr hssi_8g_rx_pcs_clock_gate_dw_rm_wr en_dw_rm_wrclk_gating hssi_8g_rx_pcs_clock_gate_dw_wa hssi_8g_rx_pcs_clock_gate_dw_wa en_dw_wa_clk_gating hssi_8g_rx_pcs_clock_gate_pc_rdclk hssi_8g_rx_pcs_clock_gate_pc_rdclk en_pc_rdclk_gating hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk en_sw_pc_wrclk_gating hssi_8g_rx_pcs_clock_gate_sw_rm_rd hssi_8g_rx_pcs_clock_gate_sw_rm_rd en_sw_rm_rdclk_gating hssi_8g_rx_pcs_clock_gate_sw_rm_wr hssi_8g_rx_pcs_clock_gate_sw_rm_wr en_sw_rm_wrclk_gating hssi_8g_rx_pcs_clock_gate_sw_wa hssi_8g_rx_pcs_clock_gate_sw_wa en_sw_wa_clk_gating hssi_8g_rx_pcs_clock_observation_in_pld_core hssi_8g_rx_pcs_clock_observation_in_pld_core internal_sw_wa_clk hssi_8g_rx_pcs_ctrl_plane_bonding_compensation hssi_8g_rx_pcs_ctrl_plane_bonding_compensation dis_compensation hssi_8g_rx_pcs_ctrl_plane_bonding_consumption hssi_8g_rx_pcs_ctrl_plane_bonding_consumption individual hssi_8g_rx_pcs_ctrl_plane_bonding_distribution hssi_8g_rx_pcs_ctrl_plane_bonding_distribution not_master_chnl_distr hssi_8g_rx_pcs_eidle_entry_eios hssi_8g_rx_pcs_eidle_entry_eios dis_eidle_eios hssi_8g_rx_pcs_eidle_entry_iei hssi_8g_rx_pcs_eidle_entry_iei dis_eidle_iei hssi_8g_rx_pcs_eidle_entry_sd hssi_8g_rx_pcs_eidle_entry_sd dis_eidle_sd hssi_8g_rx_pcs_eightb_tenb_decoder hssi_8g_rx_pcs_eightb_tenb_decoder en_8b10b_ibm hssi_8g_rx_pcs_err_flags_sel hssi_8g_rx_pcs_err_flags_sel err_flags_wa hssi_8g_rx_pcs_fixed_pat_det hssi_8g_rx_pcs_fixed_pat_det dis_fixed_patdet hssi_8g_rx_pcs_fixed_pat_num hssi_8g_rx_pcs_fixed_pat_num 0 hssi_8g_rx_pcs_force_signal_detect hssi_8g_rx_pcs_force_signal_detect en_force_signal_detect hssi_8g_rx_pcs_gen3_clk_en hssi_8g_rx_pcs_gen3_clk_en disable_clk hssi_8g_rx_pcs_gen3_rx_clk_sel hssi_8g_rx_pcs_gen3_rx_clk_sel rcvd_clk hssi_8g_rx_pcs_gen3_tx_clk_sel hssi_8g_rx_pcs_gen3_tx_clk_sel tx_pma_clk hssi_8g_rx_pcs_hip_mode hssi_8g_rx_pcs_hip_mode dis_hip hssi_8g_rx_pcs_ibm_invalid_code hssi_8g_rx_pcs_ibm_invalid_code dis_ibm_invalid_code hssi_8g_rx_pcs_invalid_code_flag_only hssi_8g_rx_pcs_invalid_code_flag_only dis_invalid_code_only hssi_8g_rx_pcs_pad_or_edb_error_replace hssi_8g_rx_pcs_pad_or_edb_error_replace replace_edb hssi_8g_rx_pcs_pcs_bypass hssi_8g_rx_pcs_pcs_bypass dis_pcs_bypass hssi_8g_rx_pcs_phase_comp_rdptr hssi_8g_rx_pcs_phase_comp_rdptr disable_rdptr hssi_8g_rx_pcs_phase_compensation_fifo hssi_8g_rx_pcs_phase_compensation_fifo register_fifo hssi_8g_rx_pcs_pipe_if_enable hssi_8g_rx_pcs_pipe_if_enable dis_pipe_rx hssi_8g_rx_pcs_pma_dw hssi_8g_rx_pcs_pma_dw ten_bit hssi_8g_rx_pcs_polinv_8b10b_dec hssi_8g_rx_pcs_polinv_8b10b_dec dis_polinv_8b10b_dec hssi_8g_rx_pcs_prot_mode hssi_8g_rx_pcs_prot_mode disabled_prot_mode hssi_8g_rx_pcs_rate_match hssi_8g_rx_pcs_rate_match dis_rm hssi_8g_rx_pcs_rate_match_del_thres hssi_8g_rx_pcs_rate_match_del_thres dis_rm_del_thres hssi_8g_rx_pcs_rate_match_empty_thres hssi_8g_rx_pcs_rate_match_empty_thres dis_rm_empty_thres hssi_8g_rx_pcs_rate_match_full_thres hssi_8g_rx_pcs_rate_match_full_thres dis_rm_full_thres hssi_8g_rx_pcs_rate_match_ins_thres hssi_8g_rx_pcs_rate_match_ins_thres dis_rm_ins_thres hssi_8g_rx_pcs_rate_match_start_thres hssi_8g_rx_pcs_rate_match_start_thres dis_rm_start_thres hssi_8g_rx_pcs_rx_clk2 hssi_8g_rx_pcs_rx_clk2 rcvd_clk_clk2 hssi_8g_rx_pcs_rx_clk_free_running hssi_8g_rx_pcs_rx_clk_free_running en_rx_clk_free_run hssi_8g_rx_pcs_rx_pcs_urst hssi_8g_rx_pcs_rx_pcs_urst en_rx_pcs_urst hssi_8g_rx_pcs_rx_rcvd_clk hssi_8g_rx_pcs_rx_rcvd_clk rcvd_clk_rcvd_clk hssi_8g_rx_pcs_rx_rd_clk hssi_8g_rx_pcs_rx_rd_clk rx_clk hssi_8g_rx_pcs_rx_refclk hssi_8g_rx_pcs_rx_refclk dis_refclk_sel hssi_8g_rx_pcs_rx_wr_clk hssi_8g_rx_pcs_rx_wr_clk rx_clk2_div_1_2_4 hssi_8g_rx_pcs_sup_mode hssi_8g_rx_pcs_sup_mode user_mode hssi_8g_rx_pcs_symbol_swap hssi_8g_rx_pcs_symbol_swap dis_symbol_swap hssi_8g_rx_pcs_sync_sm_idle_eios hssi_8g_rx_pcs_sync_sm_idle_eios dis_syncsm_idle hssi_8g_rx_pcs_test_bus_sel hssi_8g_rx_pcs_test_bus_sel tx_testbus hssi_8g_rx_pcs_tx_rx_parallel_loopback hssi_8g_rx_pcs_tx_rx_parallel_loopback dis_plpbk hssi_8g_rx_pcs_wa_boundary_lock_ctrl hssi_8g_rx_pcs_wa_boundary_lock_ctrl sync_sm hssi_8g_rx_pcs_wa_clk_slip_spacing hssi_8g_rx_pcs_wa_clk_slip_spacing 16 hssi_8g_rx_pcs_wa_det_latency_sync_status_beh hssi_8g_rx_pcs_wa_det_latency_sync_status_beh dont_care_assert_sync hssi_8g_rx_pcs_wa_disp_err_flag hssi_8g_rx_pcs_wa_disp_err_flag en_disp_err_flag hssi_8g_rx_pcs_wa_kchar hssi_8g_rx_pcs_wa_kchar dis_kchar hssi_8g_rx_pcs_wa_pd hssi_8g_rx_pcs_wa_pd wa_pd_10 hssi_8g_rx_pcs_wa_pd_data hssi_8g_rx_pcs_wa_pd_data 0 hssi_8g_rx_pcs_wa_pd_polarity hssi_8g_rx_pcs_wa_pd_polarity dont_care_both_pol hssi_8g_rx_pcs_wa_pld_controlled hssi_8g_rx_pcs_wa_pld_controlled dis_pld_ctrl hssi_8g_rx_pcs_wa_renumber_data hssi_8g_rx_pcs_wa_renumber_data 3 hssi_8g_rx_pcs_wa_rgnumber_data hssi_8g_rx_pcs_wa_rgnumber_data 3 hssi_8g_rx_pcs_wa_rknumber_data hssi_8g_rx_pcs_wa_rknumber_data 3 hssi_8g_rx_pcs_wa_rosnumber_data hssi_8g_rx_pcs_wa_rosnumber_data 1 hssi_8g_rx_pcs_wa_rvnumber_data hssi_8g_rx_pcs_wa_rvnumber_data 0 hssi_8g_rx_pcs_wa_sync_sm_ctrl hssi_8g_rx_pcs_wa_sync_sm_ctrl gige_sync_sm hssi_8g_rx_pcs_wait_cnt hssi_8g_rx_pcs_wait_cnt 0 hssi_8g_rx_pcs_silicon_rev hssi_8g_rx_pcs_silicon_rev 14nm5bcr2eb hssi_8g_rx_pcs_reconfig_settings hssi_8g_rx_pcs_reconfig_settings {} hssi_8g_tx_pcs_auto_speed_nego_gen2 hssi_8g_tx_pcs_auto_speed_nego_gen2 dis_asn_g2 hssi_8g_tx_pcs_bit_reversal hssi_8g_tx_pcs_bit_reversal dis_bit_reversal hssi_8g_tx_pcs_bonding_dft_en hssi_8g_tx_pcs_bonding_dft_en dft_dis hssi_8g_tx_pcs_bonding_dft_val hssi_8g_tx_pcs_bonding_dft_val dft_0 hssi_8g_tx_pcs_bypass_pipeline_reg hssi_8g_tx_pcs_bypass_pipeline_reg dis_bypass_pipeline hssi_8g_tx_pcs_byte_serializer hssi_8g_tx_pcs_byte_serializer dis_bs hssi_8g_tx_pcs_clock_gate_bs_enc hssi_8g_tx_pcs_clock_gate_bs_enc en_bs_enc_clk_gating hssi_8g_tx_pcs_clock_gate_dw_fifowr hssi_8g_tx_pcs_clock_gate_dw_fifowr en_dw_fifowr_clk_gating hssi_8g_tx_pcs_clock_gate_fiford hssi_8g_tx_pcs_clock_gate_fiford en_fiford_clk_gating hssi_8g_tx_pcs_clock_gate_sw_fifowr hssi_8g_tx_pcs_clock_gate_sw_fifowr en_sw_fifowr_clk_gating hssi_8g_tx_pcs_clock_observation_in_pld_core hssi_8g_tx_pcs_clock_observation_in_pld_core internal_refclk_b hssi_8g_tx_pcs_ctrl_plane_bonding_compensation hssi_8g_tx_pcs_ctrl_plane_bonding_compensation dis_compensation hssi_8g_tx_pcs_ctrl_plane_bonding_consumption hssi_8g_tx_pcs_ctrl_plane_bonding_consumption individual hssi_8g_tx_pcs_ctrl_plane_bonding_distribution hssi_8g_tx_pcs_ctrl_plane_bonding_distribution not_master_chnl_distr hssi_8g_tx_pcs_data_selection_8b10b_encoder_input hssi_8g_tx_pcs_data_selection_8b10b_encoder_input normal_data_path hssi_8g_tx_pcs_dynamic_clk_switch hssi_8g_tx_pcs_dynamic_clk_switch dis_dyn_clk_switch hssi_8g_tx_pcs_eightb_tenb_disp_ctrl hssi_8g_tx_pcs_eightb_tenb_disp_ctrl dis_disp_ctrl hssi_8g_tx_pcs_eightb_tenb_encoder hssi_8g_tx_pcs_eightb_tenb_encoder en_8b10b_ibm hssi_8g_tx_pcs_force_echar hssi_8g_tx_pcs_force_echar dis_force_echar hssi_8g_tx_pcs_force_kchar hssi_8g_tx_pcs_force_kchar dis_force_kchar hssi_8g_tx_pcs_gen3_tx_clk_sel hssi_8g_tx_pcs_gen3_tx_clk_sel dis_tx_clk hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel dis_tx_pipe_clk hssi_8g_tx_pcs_hip_mode hssi_8g_tx_pcs_hip_mode dis_hip hssi_8g_tx_pcs_pcs_bypass hssi_8g_tx_pcs_pcs_bypass dis_pcs_bypass hssi_8g_tx_pcs_phase_comp_rdptr hssi_8g_tx_pcs_phase_comp_rdptr disable_rdptr hssi_8g_tx_pcs_phase_compensation_fifo hssi_8g_tx_pcs_phase_compensation_fifo register_fifo hssi_8g_tx_pcs_phfifo_write_clk_sel hssi_8g_tx_pcs_phfifo_write_clk_sel tx_clk hssi_8g_tx_pcs_pma_dw hssi_8g_tx_pcs_pma_dw ten_bit hssi_8g_tx_pcs_prot_mode hssi_8g_tx_pcs_prot_mode disabled_prot_mode hssi_8g_tx_pcs_refclk_b_clk_sel hssi_8g_tx_pcs_refclk_b_clk_sel tx_pma_clock hssi_8g_tx_pcs_revloop_back_rm hssi_8g_tx_pcs_revloop_back_rm dis_rev_loopback_rx_rm hssi_8g_tx_pcs_sup_mode hssi_8g_tx_pcs_sup_mode user_mode hssi_8g_tx_pcs_symbol_swap hssi_8g_tx_pcs_symbol_swap dis_symbol_swap hssi_8g_tx_pcs_tx_bitslip hssi_8g_tx_pcs_tx_bitslip dis_tx_bitslip hssi_8g_tx_pcs_tx_compliance_controlled_disparity hssi_8g_tx_pcs_tx_compliance_controlled_disparity dis_txcompliance hssi_8g_tx_pcs_tx_fast_pld_reg hssi_8g_tx_pcs_tx_fast_pld_reg dis_tx_fast_pld_reg hssi_8g_tx_pcs_txclk_freerun hssi_8g_tx_pcs_txclk_freerun en_freerun_tx hssi_8g_tx_pcs_txpcs_urst hssi_8g_tx_pcs_txpcs_urst en_txpcs_urst hssi_8g_tx_pcs_silicon_rev hssi_8g_tx_pcs_silicon_rev 14nm5bcr2eb hssi_8g_tx_pcs_reconfig_settings hssi_8g_tx_pcs_reconfig_settings {} hssi_adapt_rx_adapter_lpbk_mode hssi_adapt_rx_adapter_lpbk_mode disable hssi_adapt_rx_hd_hssiadapt_aib_hssi_pld_sclk_hz hssi_adapt_rx_hd_hssiadapt_aib_hssi_pld_sclk_hz 0 hssi_adapt_rx_hd_hssiadapt_aib_hssi_rx_sr_clk_in_hz hssi_adapt_rx_hd_hssiadapt_aib_hssi_rx_sr_clk_in_hz 0 hssi_adapt_rx_aib_lpbk_mode hssi_adapt_rx_aib_lpbk_mode disable hssi_adapt_rx_align_del hssi_adapt_rx_align_del align_del_dis hssi_adapt_rx_asn_bypass_clock_gate hssi_adapt_rx_asn_bypass_clock_gate disable hssi_adapt_rx_asn_bypass_pma_pcie_sw_done hssi_adapt_rx_asn_bypass_pma_pcie_sw_done disable hssi_adapt_rx_asn_en hssi_adapt_rx_asn_en disable hssi_adapt_rx_asn_wait_for_clock_gate_cnt hssi_adapt_rx_asn_wait_for_clock_gate_cnt 32 hssi_adapt_rx_asn_wait_for_dll_reset_cnt hssi_adapt_rx_asn_wait_for_dll_reset_cnt 32 hssi_adapt_rx_asn_wait_for_fifo_flush_cnt hssi_adapt_rx_asn_wait_for_fifo_flush_cnt 32 hssi_adapt_rx_asn_wait_for_pma_pcie_sw_done_cnt hssi_adapt_rx_asn_wait_for_pma_pcie_sw_done_cnt 32 hssi_adapt_rx_async_direct_hip_en hssi_adapt_rx_async_direct_hip_en disable hssi_adapt_rx_bonding_dft_en hssi_adapt_rx_bonding_dft_en dft_dis hssi_adapt_rx_bonding_dft_val hssi_adapt_rx_bonding_dft_val dft_0 hssi_adapt_rx_chnl_bonding hssi_adapt_rx_chnl_bonding disable hssi_adapt_rx_clock_del_measure_enable hssi_adapt_rx_clock_del_measure_enable disable hssi_adapt_rx_comp_cnt hssi_adapt_rx_comp_cnt 0 hssi_adapt_rx_compin_sel hssi_adapt_rx_compin_sel compin_master hssi_adapt_rx_control_del hssi_adapt_rx_control_del control_del_none hssi_adapt_rx_hd_hssiadapt_csr_clk_hz hssi_adapt_rx_hd_hssiadapt_csr_clk_hz 0 hssi_adapt_rx_ctrl_plane_bonding hssi_adapt_rx_ctrl_plane_bonding individual hssi_adapt_rx_datapath_mapping_mode hssi_adapt_rx_datapath_mapping_mode map_10g_2x2x_2x1x_fifo hssi_adapt_rx_ds_bypass_pipeln hssi_adapt_rx_ds_bypass_pipeln ds_bypass_pipeln_dis hssi_adapt_rx_ds_last_chnl hssi_adapt_rx_ds_last_chnl ds_last_chnl hssi_adapt_rx_ds_master hssi_adapt_rx_ds_master ds_master_en hssi_adapt_rx_duplex_mode hssi_adapt_rx_duplex_mode enable hssi_adapt_rx_dyn_clk_sw_en hssi_adapt_rx_dyn_clk_sw_en disable hssi_adapt_rx_fifo_double_write hssi_adapt_rx_fifo_double_write fifo_double_write_en hssi_adapt_rx_fifo_mode hssi_adapt_rx_fifo_mode phase_comp hssi_adapt_rx_fifo_rd_clk_scg_en hssi_adapt_rx_fifo_rd_clk_scg_en disable hssi_adapt_rx_fifo_rd_clk_sel hssi_adapt_rx_fifo_rd_clk_sel fifo_rd_pma_aib_rx_clk hssi_adapt_rx_fifo_stop_rd hssi_adapt_rx_fifo_stop_rd rd_empty hssi_adapt_rx_fifo_stop_wr hssi_adapt_rx_fifo_stop_wr n_wr_full hssi_adapt_rx_fifo_width hssi_adapt_rx_fifo_width fifo_double_width hssi_adapt_rx_fifo_wr_clk_scg_en hssi_adapt_rx_fifo_wr_clk_scg_en disable hssi_adapt_rx_fifo_wr_clk_sel hssi_adapt_rx_fifo_wr_clk_sel fifo_wr_pld_pcs_rx_clk_out hssi_adapt_rx_force_align hssi_adapt_rx_force_align force_align_dis hssi_adapt_rx_free_run_div_clk hssi_adapt_rx_free_run_div_clk out_of_reset_sync hssi_adapt_rx_fsr_pld_10g_rx_crc32_err_rst_val hssi_adapt_rx_fsr_pld_10g_rx_crc32_err_rst_val reset_to_zero_crc32 hssi_adapt_rx_fsr_pld_8g_sigdet_out_rst_val hssi_adapt_rx_fsr_pld_8g_sigdet_out_rst_val reset_to_zero_sigdet hssi_adapt_rx_fsr_pld_ltd_b_rst_val hssi_adapt_rx_fsr_pld_ltd_b_rst_val reset_to_one_ltdb hssi_adapt_rx_fsr_pld_ltr_rst_val hssi_adapt_rx_fsr_pld_ltr_rst_val reset_to_zero_ltr hssi_adapt_rx_fsr_pld_rx_fifo_align_clr_rst_val hssi_adapt_rx_fsr_pld_rx_fifo_align_clr_rst_val reset_to_zero_alignclr hssi_adapt_rx_hd_hssiadapt_hip_aib_clk_2x_hz hssi_adapt_rx_hd_hssiadapt_hip_aib_clk_2x_hz 0 hssi_adapt_rx_hd_hssiadapt_hip_aib_clk_hz hssi_adapt_rx_hd_hssiadapt_hip_aib_clk_hz 0 hssi_adapt_rx_hip_mode hssi_adapt_rx_hip_mode disable_hip hssi_adapt_rx_hrdrst_dcd_cal_done_bypass hssi_adapt_rx_hrdrst_dcd_cal_done_bypass disable hssi_adapt_rx_hrdrst_rst_sm_dis hssi_adapt_rx_hrdrst_rst_sm_dis enable_rx_rst_sm hssi_adapt_rx_hrdrst_rx_osc_clk_scg_en hssi_adapt_rx_hrdrst_rx_osc_clk_scg_en disable hssi_adapt_rx_hrdrst_user_ctl_en hssi_adapt_rx_hrdrst_user_ctl_en disable hssi_adapt_rx_indv hssi_adapt_rx_indv indv_en hssi_adapt_rx_internal_clk1_sel hssi_adapt_rx_internal_clk1_sel pld_pma_tx_clk_out_clk1 hssi_adapt_rx_internal_clk1_sel0 hssi_adapt_rx_internal_clk1_sel0 pma_clks_or_txfifowr_post_ct_or_txfiford_pre_or_post_ct_mux_clk1_mux0 hssi_adapt_rx_internal_clk1_sel1 hssi_adapt_rx_internal_clk1_sel1 pma_clks_or_txfiford_pre_or_post_ct_mux_clk1_mux1 hssi_adapt_rx_internal_clk1_sel2 hssi_adapt_rx_internal_clk1_sel2 pma_clks_or_txfiford_pre_ct_mux_clk1_mux2 hssi_adapt_rx_internal_clk1_sel3 hssi_adapt_rx_internal_clk1_sel3 pma_clks_clk1_mux3 hssi_adapt_rx_internal_clk2_sel hssi_adapt_rx_internal_clk2_sel pld_pma_tx_clk_out_clk2 hssi_adapt_rx_internal_clk2_sel0 hssi_adapt_rx_internal_clk2_sel0 pma_clks_or_rxfiford_post_ct_or_rxfifowr_pre_or_post_ct_mux_clk2_mux0 hssi_adapt_rx_internal_clk2_sel1 hssi_adapt_rx_internal_clk2_sel1 pma_clks_or_rxfifowr_pre_or_post_ct_mux_clk2_mux1 hssi_adapt_rx_internal_clk2_sel2 hssi_adapt_rx_internal_clk2_sel2 pma_clks_or_rxfifowr_pre_ct_mux_clk2_mux2 hssi_adapt_rx_internal_clk2_sel3 hssi_adapt_rx_internal_clk2_sel3 pma_clks_clk2_mux3 hssi_adapt_rx_loopback_mode hssi_adapt_rx_loopback_mode loopback_disable hssi_adapt_rx_osc_clk_scg_en hssi_adapt_rx_osc_clk_scg_en disable hssi_adapt_rx_phcomp_rd_del hssi_adapt_rx_phcomp_rd_del phcomp_rd_del3 hssi_adapt_rx_pipe_mode hssi_adapt_rx_pipe_mode disable_pipe hssi_adapt_rx_hd_hssiadapt_pld_pcs_rx_clk_out_hz hssi_adapt_rx_hd_hssiadapt_pld_pcs_rx_clk_out_hz 161132812 hssi_adapt_rx_hd_hssiadapt_pld_pma_hclk_hz hssi_adapt_rx_hd_hssiadapt_pld_pma_hclk_hz 0 hssi_adapt_rx_pma_aib_rx_clk_expected_setting hssi_adapt_rx_pma_aib_rx_clk_expected_setting x2 hssi_adapt_rx_hd_hssiadapt_pma_aib_rx_clk_hz hssi_adapt_rx_hd_hssiadapt_pma_aib_rx_clk_hz 0 hssi_adapt_rx_pma_coreclkin_sel hssi_adapt_rx_pma_coreclkin_sel pma_coreclkin_pld_sel hssi_adapt_rx_pma_hclk_scg_en hssi_adapt_rx_pma_hclk_scg_en enable hssi_adapt_rx_powerdown_mode hssi_adapt_rx_powerdown_mode powerup hssi_adapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass hssi_adapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass disable hssi_adapt_rx_rx_adp_go_b4txeq_en hssi_adapt_rx_rx_adp_go_b4txeq_en enable hssi_adapt_rx_rx_datapath_tb_sel hssi_adapt_rx_rx_datapath_tb_sel cp_bond hssi_adapt_rx_rx_eq_iteration hssi_adapt_rx_rx_eq_iteration cycles_32 hssi_adapt_rx_rx_fifo_power_mode hssi_adapt_rx_rx_fifo_power_mode full_width_full_depth hssi_adapt_rx_rx_fifo_read_latency_adjust hssi_adapt_rx_rx_fifo_read_latency_adjust disable hssi_adapt_rx_rx_fifo_write_latency_adjust hssi_adapt_rx_rx_fifo_write_latency_adjust disable hssi_adapt_rx_rx_invalid_no_change hssi_adapt_rx_rx_invalid_no_change disable hssi_adapt_rx_rx_osc_clock_setting hssi_adapt_rx_rx_osc_clock_setting osc_clk_div_by1 hssi_adapt_rx_rx_parity_sel hssi_adapt_rx_rx_parity_sel func_sel hssi_adapt_rx_rx_pcs_testbus_sel hssi_adapt_rx_rx_pcs_testbus_sel direct_tr_tb_bit0_sel hssi_adapt_rx_rx_pcspma_testbus_sel hssi_adapt_rx_rx_pcspma_testbus_sel enable hssi_adapt_rx_rx_pld_8g_a1a2_k1k2_flag_polling_bypass hssi_adapt_rx_rx_pld_8g_a1a2_k1k2_flag_polling_bypass disable hssi_adapt_rx_rx_pld_8g_wa_boundary_polling_bypass hssi_adapt_rx_rx_pld_8g_wa_boundary_polling_bypass disable hssi_adapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass hssi_adapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass disable hssi_adapt_rx_rx_pld_pma_reser_in_polling_bypass hssi_adapt_rx_rx_pld_pma_reser_in_polling_bypass disable hssi_adapt_rx_rx_pld_pma_testbus_polling_bypass hssi_adapt_rx_rx_pld_pma_testbus_polling_bypass disable hssi_adapt_rx_rx_pld_test_data_polling_bypass hssi_adapt_rx_rx_pld_test_data_polling_bypass disable hssi_adapt_rx_rx_pma_rstn_cycles hssi_adapt_rx_rx_pma_rstn_cycles four_cycles hssi_adapt_rx_rx_pma_rstn_en hssi_adapt_rx_rx_pma_rstn_en disable hssi_adapt_rx_rx_post_cursor_en hssi_adapt_rx_rx_post_cursor_en disable hssi_adapt_rx_rx_pre_cursor_en hssi_adapt_rx_rx_pre_cursor_en disable hssi_adapt_rx_rx_rmfflag_stretch_enable hssi_adapt_rx_rx_rmfflag_stretch_enable enable hssi_adapt_rx_rx_rmfflag_stretch_num_stages hssi_adapt_rx_rx_rmfflag_stretch_num_stages rmfflag_two_stage hssi_adapt_rx_rx_rxeq_en hssi_adapt_rx_rx_rxeq_en disable hssi_adapt_rx_rx_txeq_en hssi_adapt_rx_rx_txeq_en disable hssi_adapt_rx_rx_txeq_time hssi_adapt_rx_rx_txeq_time 64 hssi_adapt_rx_rx_use_rxvalid_for_rxeq hssi_adapt_rx_rx_use_rxvalid_for_rxeq rxvalid hssi_adapt_rx_rx_usertest_sel hssi_adapt_rx_rx_usertest_sel direct_tr_usertest3_sel hssi_adapt_rx_rxfifo_empty hssi_adapt_rx_rxfifo_empty empty_default hssi_adapt_rx_rxfifo_full hssi_adapt_rx_rxfifo_full full_dw hssi_adapt_rx_rxfifo_mode hssi_adapt_rx_rxfifo_mode rxphase_comp hssi_adapt_rx_rxfifo_pempty hssi_adapt_rx_rxfifo_pempty 2 hssi_adapt_rx_rxfifo_pfull hssi_adapt_rx_rxfifo_pfull 5 hssi_adapt_rx_rxfiford_post_ct_sel hssi_adapt_rx_rxfiford_post_ct_sel rxfiford_sclk_post_ct hssi_adapt_rx_rxfiford_to_aib_sel hssi_adapt_rx_rxfiford_to_aib_sel rxfiford_sclk_to_aib hssi_adapt_rx_rxfifowr_post_ct_sel hssi_adapt_rx_rxfifowr_post_ct_sel rxfifowr_sclk_post_ct hssi_adapt_rx_rxfifowr_pre_ct_sel hssi_adapt_rx_rxfifowr_pre_ct_sel rxfifowr_sclk_pre_ct hssi_adapt_rx_slv_asn_en hssi_adapt_rx_slv_asn_en disable hssi_adapt_rx_hd_hssiadapt_speed_grade hssi_adapt_rx_hd_hssiadapt_speed_grade dash_2 hssi_adapt_rx_stretch_num_stages hssi_adapt_rx_stretch_num_stages seven_stage hssi_adapt_rx_sup_mode hssi_adapt_rx_sup_mode user_mode hssi_adapt_rx_txeq_clk_scg_en hssi_adapt_rx_txeq_clk_scg_en enable hssi_adapt_rx_txeq_clk_sel hssi_adapt_rx_txeq_clk_sel txeq_pld_pcs_rx_clk_out hssi_adapt_rx_txeq_mode hssi_adapt_rx_txeq_mode eq_disable hssi_adapt_rx_txeq_rst_sel hssi_adapt_rx_txeq_rst_sel txeq_pcs_rx_pld_rst_n hssi_adapt_rx_txfiford_post_ct_sel hssi_adapt_rx_txfiford_post_ct_sel txfiford_sclk_post_ct hssi_adapt_rx_txfiford_pre_ct_sel hssi_adapt_rx_txfiford_pre_ct_sel txfiford_sclk_pre_ct hssi_adapt_rx_txfifowr_from_aib_sel hssi_adapt_rx_txfifowr_from_aib_sel txfifowr_sclk_from_aib hssi_adapt_rx_txfifowr_post_ct_sel hssi_adapt_rx_txfifowr_post_ct_sel txfifowr_sclk_post_ct hssi_adapt_rx_us_bypass_pipeln hssi_adapt_rx_us_bypass_pipeln us_bypass_pipeln_dis hssi_adapt_rx_us_last_chnl hssi_adapt_rx_us_last_chnl us_last_chnl hssi_adapt_rx_us_master hssi_adapt_rx_us_master us_master_en hssi_adapt_rx_word_align_enable hssi_adapt_rx_word_align_enable enable hssi_adapt_rx_word_mark hssi_adapt_rx_word_mark wm_en hssi_adapt_rx_silicon_rev hssi_adapt_rx_silicon_rev 14nm5bcr2eb hssi_adapt_tx_aib_clk_sel hssi_adapt_tx_aib_clk_sel aib_clk_pma_aib_tx_clk hssi_adapt_tx_hd_hssiadapt_aib_hssi_pld_sclk_hz hssi_adapt_tx_hd_hssiadapt_aib_hssi_pld_sclk_hz 0 hssi_adapt_tx_hd_hssiadapt_aib_hssi_tx_sr_clk_in_hz hssi_adapt_tx_hd_hssiadapt_aib_hssi_tx_sr_clk_in_hz 0 hssi_adapt_tx_hd_hssiadapt_aib_hssi_tx_transfer_clk_hz hssi_adapt_tx_hd_hssiadapt_aib_hssi_tx_transfer_clk_hz 322265624 hssi_adapt_tx_bonding_dft_en hssi_adapt_tx_bonding_dft_en dft_dis hssi_adapt_tx_bonding_dft_val hssi_adapt_tx_bonding_dft_val dft_0 hssi_adapt_tx_chnl_bonding hssi_adapt_tx_chnl_bonding disable hssi_adapt_tx_comp_cnt hssi_adapt_tx_comp_cnt 0 hssi_adapt_tx_compin_sel hssi_adapt_tx_compin_sel compin_master hssi_adapt_tx_hd_hssiadapt_csr_clk_hz hssi_adapt_tx_hd_hssiadapt_csr_clk_hz 0 hssi_adapt_tx_ctrl_plane_bonding hssi_adapt_tx_ctrl_plane_bonding individual hssi_adapt_tx_datapath_mapping_mode hssi_adapt_tx_datapath_mapping_mode map_10g_2x2x_2x1x_fifo hssi_adapt_tx_ds_bypass_pipeln hssi_adapt_tx_ds_bypass_pipeln ds_bypass_pipeln_dis hssi_adapt_tx_ds_last_chnl hssi_adapt_tx_ds_last_chnl ds_last_chnl hssi_adapt_tx_ds_master hssi_adapt_tx_ds_master ds_master_en hssi_adapt_tx_duplex_mode hssi_adapt_tx_duplex_mode enable hssi_adapt_tx_dv_gating hssi_adapt_tx_dv_gating disable hssi_adapt_tx_dyn_clk_sw_en hssi_adapt_tx_dyn_clk_sw_en disable hssi_adapt_tx_fifo_double_read hssi_adapt_tx_fifo_double_read fifo_double_read_en hssi_adapt_tx_fifo_mode hssi_adapt_tx_fifo_mode phase_comp hssi_adapt_tx_fifo_rd_clk_scg_en hssi_adapt_tx_fifo_rd_clk_scg_en disable hssi_adapt_tx_fifo_rd_clk_sel hssi_adapt_tx_fifo_rd_clk_sel fifo_rd_pld_pcs_tx_clk_out hssi_adapt_tx_fifo_ready_bypass hssi_adapt_tx_fifo_ready_bypass disable hssi_adapt_tx_fifo_stop_rd hssi_adapt_tx_fifo_stop_rd rd_empty hssi_adapt_tx_fifo_stop_wr hssi_adapt_tx_fifo_stop_wr wr_full hssi_adapt_tx_fifo_width hssi_adapt_tx_fifo_width fifo_double_width hssi_adapt_tx_fifo_wr_clk_scg_en hssi_adapt_tx_fifo_wr_clk_scg_en disable hssi_adapt_tx_free_run_div_clk hssi_adapt_tx_free_run_div_clk out_of_reset_sync hssi_adapt_tx_fsr_hip_fsr_in_bit0_rst_val hssi_adapt_tx_fsr_hip_fsr_in_bit0_rst_val reset_to_one_hfsrin0 hssi_adapt_tx_fsr_hip_fsr_in_bit1_rst_val hssi_adapt_tx_fsr_hip_fsr_in_bit1_rst_val reset_to_one_hfsrin1 hssi_adapt_tx_fsr_hip_fsr_in_bit2_rst_val hssi_adapt_tx_fsr_hip_fsr_in_bit2_rst_val reset_to_one_hfsrin2 hssi_adapt_tx_fsr_hip_fsr_in_bit3_rst_val hssi_adapt_tx_fsr_hip_fsr_in_bit3_rst_val reset_to_zero_hfsrin3 hssi_adapt_tx_fsr_hip_fsr_out_bit0_rst_val hssi_adapt_tx_fsr_hip_fsr_out_bit0_rst_val reset_to_one_hfsrout0 hssi_adapt_tx_fsr_hip_fsr_out_bit1_rst_val hssi_adapt_tx_fsr_hip_fsr_out_bit1_rst_val reset_to_one_hfsrout1 hssi_adapt_tx_fsr_hip_fsr_out_bit2_rst_val hssi_adapt_tx_fsr_hip_fsr_out_bit2_rst_val reset_to_zero_hfsrout2 hssi_adapt_tx_fsr_hip_fsr_out_bit3_rst_val hssi_adapt_tx_fsr_hip_fsr_out_bit3_rst_val reset_to_zero_hfsrout3 hssi_adapt_tx_fsr_mask_tx_pll_rst_val hssi_adapt_tx_fsr_mask_tx_pll_rst_val reset_to_zero_maskpll hssi_adapt_tx_fsr_pld_txelecidle_rst_val hssi_adapt_tx_fsr_pld_txelecidle_rst_val reset_to_zero_txelec hssi_adapt_tx_hd_hssiadapt_hip_aib_clk_2x_hz hssi_adapt_tx_hd_hssiadapt_hip_aib_clk_2x_hz 0 hssi_adapt_tx_hd_hssiadapt_hip_aib_clk_hz hssi_adapt_tx_hd_hssiadapt_hip_aib_clk_hz 0 hssi_adapt_tx_hd_hssiadapt_hip_aib_txeq_clk_out_hz hssi_adapt_tx_hd_hssiadapt_hip_aib_txeq_clk_out_hz 0 hssi_adapt_tx_hip_mode hssi_adapt_tx_hip_mode disable_hip hssi_adapt_tx_hip_osc_clk_scg_en hssi_adapt_tx_hip_osc_clk_scg_en enable hssi_adapt_tx_hrdrst_align_bypass hssi_adapt_tx_hrdrst_align_bypass enable hssi_adapt_tx_hrdrst_dcd_cal_done_bypass hssi_adapt_tx_hrdrst_dcd_cal_done_bypass disable hssi_adapt_tx_hrdrst_dll_lock_bypass hssi_adapt_tx_hrdrst_dll_lock_bypass disable hssi_adapt_tx_hrdrst_rst_sm_dis hssi_adapt_tx_hrdrst_rst_sm_dis enable_tx_rst_sm hssi_adapt_tx_hrdrst_rx_osc_clk_scg_en hssi_adapt_tx_hrdrst_rx_osc_clk_scg_en disable hssi_adapt_tx_hrdrst_user_ctl_en hssi_adapt_tx_hrdrst_user_ctl_en disable hssi_adapt_tx_indv hssi_adapt_tx_indv indv_en hssi_adapt_tx_loopback_mode hssi_adapt_tx_loopback_mode loopback_disable hssi_adapt_tx_osc_clk_scg_en hssi_adapt_tx_osc_clk_scg_en disable hssi_adapt_tx_phcomp_rd_del hssi_adapt_tx_phcomp_rd_del phcomp_rd_del2 hssi_adapt_tx_pipe_mode hssi_adapt_tx_pipe_mode disable_pipe hssi_adapt_tx_hd_hssiadapt_pld_pcs_tx_clk_out_hz hssi_adapt_tx_hd_hssiadapt_pld_pcs_tx_clk_out_hz 161132812 hssi_adapt_tx_hd_hssiadapt_pld_pma_hclk_hz hssi_adapt_tx_hd_hssiadapt_pld_pma_hclk_hz 0 hssi_adapt_tx_pma_aib_tx_clk_expected_setting hssi_adapt_tx_pma_aib_tx_clk_expected_setting x2 hssi_adapt_tx_hd_hssiadapt_pma_aib_tx_clk_hz hssi_adapt_tx_hd_hssiadapt_pma_aib_tx_clk_hz 0 hssi_adapt_tx_powerdown_mode hssi_adapt_tx_powerdown_mode powerup hssi_adapt_tx_presethint_bypass hssi_adapt_tx_presethint_bypass enable hssi_adapt_tx_qpi_sr_enable hssi_adapt_tx_qpi_sr_enable enable hssi_adapt_tx_rxqpi_pullup_rst_val hssi_adapt_tx_rxqpi_pullup_rst_val reset_to_zero_rxqpi hssi_adapt_tx_hd_hssiadapt_speed_grade hssi_adapt_tx_hd_hssiadapt_speed_grade dash_2 hssi_adapt_tx_stretch_num_stages hssi_adapt_tx_stretch_num_stages seven_stage hssi_adapt_tx_sup_mode hssi_adapt_tx_sup_mode user_mode hssi_adapt_tx_tx_datapath_tb_sel hssi_adapt_tx_tx_datapath_tb_sel cp_bond hssi_adapt_tx_tx_fastbond_wren hssi_adapt_tx_tx_fastbond_wren wren_ds_del2_us_del2 hssi_adapt_tx_tx_fifo_power_mode hssi_adapt_tx_tx_fifo_power_mode full_width_full_depth hssi_adapt_tx_tx_fifo_read_latency_adjust hssi_adapt_tx_tx_fifo_read_latency_adjust disable hssi_adapt_tx_tx_fifo_write_latency_adjust hssi_adapt_tx_tx_fifo_write_latency_adjust disable hssi_adapt_tx_tx_osc_clock_setting hssi_adapt_tx_tx_osc_clock_setting osc_clk_div_by1 hssi_adapt_tx_tx_qpi_mode_en hssi_adapt_tx_tx_qpi_mode_en disable hssi_adapt_tx_tx_rev_lpbk hssi_adapt_tx_tx_rev_lpbk disable hssi_adapt_tx_tx_usertest_sel hssi_adapt_tx_tx_usertest_sel enable hssi_adapt_tx_txfifo_empty hssi_adapt_tx_txfifo_empty empty_default hssi_adapt_tx_txfifo_full hssi_adapt_tx_txfifo_full full_dw hssi_adapt_tx_txfifo_mode hssi_adapt_tx_txfifo_mode txphase_comp hssi_adapt_tx_txfifo_pempty hssi_adapt_tx_txfifo_pempty 2 hssi_adapt_tx_txfifo_pfull hssi_adapt_tx_txfifo_pfull 5 hssi_adapt_tx_txqpi_pulldn_rst_val hssi_adapt_tx_txqpi_pulldn_rst_val reset_to_zero_txqpid hssi_adapt_tx_txqpi_pullup_rst_val hssi_adapt_tx_txqpi_pullup_rst_val reset_to_zero_txqpiu hssi_adapt_tx_us_last_chnl hssi_adapt_tx_us_last_chnl us_last_chnl hssi_adapt_tx_us_master hssi_adapt_tx_us_master us_master_en hssi_adapt_tx_word_align hssi_adapt_tx_word_align wa_en hssi_adapt_tx_word_align_enable hssi_adapt_tx_word_align_enable enable hssi_adapt_tx_silicon_rev hssi_adapt_tx_silicon_rev 14nm5bcr2eb hssi_aibcr_rx_aib_datasel_gr0 hssi_aibcr_rx_aib_datasel_gr0 aib_datasel0_setting0 hssi_aibcr_rx_aib_datasel_gr1 hssi_aibcr_rx_aib_datasel_gr1 aib_datasel1_setting0 hssi_aibcr_rx_aib_datasel_gr2 hssi_aibcr_rx_aib_datasel_gr2 aib_datasel2_setting1 hssi_aibcr_rx_aib_ddrctrl_gr0 hssi_aibcr_rx_aib_ddrctrl_gr0 aib_ddr0_setting1 hssi_aibcr_rx_aib_ddrctrl_gr1 hssi_aibcr_rx_aib_ddrctrl_gr1 aib_ddr1_setting1 hssi_aibcr_rx_aib_iinasyncen hssi_aibcr_rx_aib_iinasyncen aib_inasyncen_setting2 hssi_aibcr_rx_aib_iinclken hssi_aibcr_rx_aib_iinclken aib_inclken_setting3 hssi_aibcr_rx_aib_outctrl_gr0 hssi_aibcr_rx_aib_outctrl_gr0 aib_outen0_setting1 hssi_aibcr_rx_aib_outctrl_gr1 hssi_aibcr_rx_aib_outctrl_gr1 aib_outen1_setting1 hssi_aibcr_rx_aib_outctrl_gr2 hssi_aibcr_rx_aib_outctrl_gr2 aib_outen2_setting1 hssi_aibcr_rx_aib_outctrl_gr3 hssi_aibcr_rx_aib_outctrl_gr3 aib_outen3_setting1 hssi_aibcr_rx_aib_outndrv_r12 hssi_aibcr_rx_aib_outndrv_r12 aib_ndrv12_setting1 hssi_aibcr_rx_aib_outndrv_r56 hssi_aibcr_rx_aib_outndrv_r56 aib_ndrv56_setting1 hssi_aibcr_rx_aib_outndrv_r78 hssi_aibcr_rx_aib_outndrv_r78 aib_ndrv78_setting1 hssi_aibcr_rx_aib_outpdrv_r12 hssi_aibcr_rx_aib_outpdrv_r12 aib_pdrv12_setting1 hssi_aibcr_rx_aib_outpdrv_r56 hssi_aibcr_rx_aib_outpdrv_r56 aib_pdrv56_setting1 hssi_aibcr_rx_aib_outpdrv_r78 hssi_aibcr_rx_aib_outpdrv_r78 aib_pdrv78_setting1 hssi_aibcr_rx_aib_red_rx_shiften hssi_aibcr_rx_aib_red_rx_shiften aib_red_rx_shift_disable hssi_aibcr_rx_aib_rx_clkdiv hssi_aibcr_rx_aib_rx_clkdiv aib_rx_clkdiv_setting1 hssi_aibcr_rx_aib_rx_dcc_byp hssi_aibcr_rx_aib_rx_dcc_byp aib_rx_dcc_byp_enable hssi_aibcr_rx_aib_rx_dcc_byp_iocsr_unused hssi_aibcr_rx_aib_rx_dcc_byp_iocsr_unused aib_rx_dcc_byp_disable_iocsr_unused hssi_aibcr_rx_aib_rx_dcc_cont_cal hssi_aibcr_rx_aib_rx_dcc_cont_cal aib_rx_dcc_cal_cont hssi_aibcr_rx_aib_rx_dcc_cont_cal_iocsr_unused hssi_aibcr_rx_aib_rx_dcc_cont_cal_iocsr_unused aib_rx_dcc_cal_single_iocsr_unused hssi_aibcr_rx_aib_rx_dcc_dft hssi_aibcr_rx_aib_rx_dcc_dft aib_rx_dcc_dft_disable hssi_aibcr_rx_aib_rx_dcc_dft_sel hssi_aibcr_rx_aib_rx_dcc_dft_sel aib_rx_dcc_dft_mode0 hssi_aibcr_rx_aib_rx_dcc_dll_entest hssi_aibcr_rx_aib_rx_dcc_dll_entest aib_rx_dcc_dll_test_disable hssi_aibcr_rx_aib_rx_dcc_dy_ctl_static hssi_aibcr_rx_aib_rx_dcc_dy_ctl_static aib_rx_dcc_dy_ctl_static_setting1 hssi_aibcr_rx_aib_rx_dcc_dy_ctlsel hssi_aibcr_rx_aib_rx_dcc_dy_ctlsel aib_rx_dcc_dy_ctlsel_setting0 hssi_aibcr_rx_aib_rx_dcc_en hssi_aibcr_rx_aib_rx_dcc_en aib_rx_dcc_disable hssi_aibcr_rx_aib_rx_dcc_en_iocsr_unused hssi_aibcr_rx_aib_rx_dcc_en_iocsr_unused aib_rx_dcc_disable_iocsr_unused hssi_aibcr_rx_aib_rx_dcc_manual_dn hssi_aibcr_rx_aib_rx_dcc_manual_dn aib_rx_dcc_manual_dn0 hssi_aibcr_rx_aib_rx_dcc_manual_up hssi_aibcr_rx_aib_rx_dcc_manual_up aib_rx_dcc_manual_up0 hssi_aibcr_rx_aib_rx_dcc_rst_prgmnvrt hssi_aibcr_rx_aib_rx_dcc_rst_prgmnvrt aib_rx_dcc_st_rst_prgmnvrt_setting0 hssi_aibcr_rx_aib_rx_dcc_st_core_dn_prgmnvrt hssi_aibcr_rx_aib_rx_dcc_st_core_dn_prgmnvrt aib_rx_dcc_st_core_dn_prgmnvrt_setting0 hssi_aibcr_rx_aib_rx_dcc_st_core_up_prgmnvrt hssi_aibcr_rx_aib_rx_dcc_st_core_up_prgmnvrt aib_rx_dcc_st_core_up_prgmnvrt_setting0 hssi_aibcr_rx_aib_rx_dcc_st_core_updnen hssi_aibcr_rx_aib_rx_dcc_st_core_updnen aib_rx_dcc_st_core_updnen_setting0 hssi_aibcr_rx_aib_rx_dcc_st_dftmuxsel hssi_aibcr_rx_aib_rx_dcc_st_dftmuxsel aib_rx_dcc_st_dftmuxsel_setting0 hssi_aibcr_rx_aib_rx_dcc_st_dly_pst hssi_aibcr_rx_aib_rx_dcc_st_dly_pst aib_rx_dcc_st_dly_pst_setting0 hssi_aibcr_rx_aib_rx_dcc_st_en hssi_aibcr_rx_aib_rx_dcc_st_en aib_rx_dcc_st_en_setting1 hssi_aibcr_rx_aib_rx_dcc_st_lockreq_muxsel hssi_aibcr_rx_aib_rx_dcc_st_lockreq_muxsel aib_rx_dcc_st_lockreq_muxsel_setting0 hssi_aibcr_rx_aib_rx_dcc_st_new_dll hssi_aibcr_rx_aib_rx_dcc_st_new_dll aib_rx_dcc_new_dll_setting0 hssi_aibcr_rx_aib_rx_dcc_st_new_dll2 hssi_aibcr_rx_aib_rx_dcc_st_new_dll2 aib_rx_dcc_new_dll2_setting0 hssi_aibcr_rx_aib_rx_dcc_st_rst hssi_aibcr_rx_aib_rx_dcc_st_rst aib_rx_dcc_st_rst_setting0 hssi_aibcr_rx_aib_rx_dcc_test_clk_pll_en_n hssi_aibcr_rx_aib_rx_dcc_test_clk_pll_en_n aib_rx_dcc_test_clk_pll_en_n_disable hssi_aibcr_rx_aib_rx_halfcode hssi_aibcr_rx_aib_rx_halfcode aib_rx_halfcode_enable hssi_aibcr_rx_aib_rx_selflock hssi_aibcr_rx_aib_rx_selflock aib_rx_selflock_enable hssi_aibcr_rx_dft_hssitestip_dll_dcc_en hssi_aibcr_rx_dft_hssitestip_dll_dcc_en disable_dft hssi_aibcr_rx_op_mode hssi_aibcr_rx_op_mode rx_dcc_disable hssi_aibcr_rx_powermode_ac hssi_aibcr_rx_powermode_ac rxdatapath_low_speed_pwr hssi_aibcr_rx_powermode_dc hssi_aibcr_rx_powermode_dc powerup hssi_aibcr_rx_redundancy_en hssi_aibcr_rx_redundancy_en disable hssi_aibcr_rx_sup_mode hssi_aibcr_rx_sup_mode user_mode hssi_aibcr_rx_silicon_rev hssi_aibcr_rx_silicon_rev 14nm5bcr2eb hssi_aibcr_tx_aib_datasel_gr0 hssi_aibcr_tx_aib_datasel_gr0 aib_datasel0_setting0 hssi_aibcr_tx_aib_datasel_gr1 hssi_aibcr_tx_aib_datasel_gr1 aib_datasel1_setting1 hssi_aibcr_tx_aib_datasel_gr2 hssi_aibcr_tx_aib_datasel_gr2 aib_datasel2_setting0 hssi_aibcr_tx_aib_dllstr_align_clkdiv hssi_aibcr_tx_aib_dllstr_align_clkdiv aib_dllstr_align_clkdiv_setting1 hssi_aibcr_tx_aib_dllstr_align_dcc_dll_dft_sel hssi_aibcr_tx_aib_dllstr_align_dcc_dll_dft_sel aib_dllstr_align_dcc_dll_dft_sel_setting0 hssi_aibcr_tx_aib_dllstr_align_dft_ch_muxsel hssi_aibcr_tx_aib_dllstr_align_dft_ch_muxsel aib_dllstr_align_dft_ch_muxsel_setting0 hssi_aibcr_tx_aib_dllstr_align_dly_pst hssi_aibcr_tx_aib_dllstr_align_dly_pst aib_dllstr_align_dly_pst_setting0 hssi_aibcr_tx_aib_dllstr_align_dy_ctl_static hssi_aibcr_tx_aib_dllstr_align_dy_ctl_static aib_dllstr_align_dy_ctl_static_setting1 hssi_aibcr_tx_aib_dllstr_align_dy_ctlsel hssi_aibcr_tx_aib_dllstr_align_dy_ctlsel aib_dllstr_align_dy_ctlsel_setting1 hssi_aibcr_tx_aib_dllstr_align_entest hssi_aibcr_tx_aib_dllstr_align_entest aib_dllstr_align_test_disable hssi_aibcr_tx_aib_dllstr_align_halfcode hssi_aibcr_tx_aib_dllstr_align_halfcode aib_dllstr_align_halfcode_enable hssi_aibcr_tx_aib_dllstr_align_selflock hssi_aibcr_tx_aib_dllstr_align_selflock aib_dllstr_align_selflock_enable hssi_aibcr_tx_aib_dllstr_align_st_core_dn_prgmnvrt hssi_aibcr_tx_aib_dllstr_align_st_core_dn_prgmnvrt aib_dllstr_align_st_core_dn_prgmnvrt_setting0 hssi_aibcr_tx_aib_dllstr_align_st_core_up_prgmnvrt hssi_aibcr_tx_aib_dllstr_align_st_core_up_prgmnvrt aib_dllstr_align_st_core_up_prgmnvrt_setting0 hssi_aibcr_tx_aib_dllstr_align_st_core_updnen hssi_aibcr_tx_aib_dllstr_align_st_core_updnen aib_dllstr_align_st_core_updnen_setting0 hssi_aibcr_tx_aib_dllstr_align_st_dftmuxsel hssi_aibcr_tx_aib_dllstr_align_st_dftmuxsel aib_dllstr_align_st_dftmuxsel_setting0 hssi_aibcr_tx_aib_dllstr_align_st_en hssi_aibcr_tx_aib_dllstr_align_st_en aib_dllstr_align_st_en_setting1 hssi_aibcr_tx_aib_dllstr_align_st_lockreq_muxsel hssi_aibcr_tx_aib_dllstr_align_st_lockreq_muxsel aib_dllstr_align_st_lockreq_muxsel_setting0 hssi_aibcr_tx_aib_dllstr_align_st_new_dll hssi_aibcr_tx_aib_dllstr_align_st_new_dll aib_dllstr_align_new_dll_setting0 hssi_aibcr_tx_aib_dllstr_align_st_new_dll2 hssi_aibcr_tx_aib_dllstr_align_st_new_dll2 aib_dllstr_align_new_dll2_setting0 hssi_aibcr_tx_aib_dllstr_align_st_rst hssi_aibcr_tx_aib_dllstr_align_st_rst aib_dllstr_align_st_rst_setting0 hssi_aibcr_tx_aib_dllstr_align_st_rst_prgmnvrt hssi_aibcr_tx_aib_dllstr_align_st_rst_prgmnvrt aib_dllstr_align_st_rst_prgmnvrt_setting0 hssi_aibcr_tx_aib_dllstr_align_test_clk_pll_en_n hssi_aibcr_tx_aib_dllstr_align_test_clk_pll_en_n aib_dllstr_align_test_clk_pll_en_n_disable hssi_aibcr_tx_aib_inctrl_gr0 hssi_aibcr_tx_aib_inctrl_gr0 aib_inctrl0_setting1 hssi_aibcr_tx_aib_inctrl_gr1 hssi_aibcr_tx_aib_inctrl_gr1 aib_inctrl1_setting3 hssi_aibcr_tx_aib_inctrl_gr2 hssi_aibcr_tx_aib_inctrl_gr2 aib_inctrl2_setting2 hssi_aibcr_tx_aib_inctrl_gr3 hssi_aibcr_tx_aib_inctrl_gr3 aib_inctrl3_setting2 hssi_aibcr_tx_aib_outctrl_gr0 hssi_aibcr_tx_aib_outctrl_gr0 aib_outen0_setting1 hssi_aibcr_tx_aib_outctrl_gr1 hssi_aibcr_tx_aib_outctrl_gr1 aib_outen1_setting1 hssi_aibcr_tx_aib_outctrl_gr2 hssi_aibcr_tx_aib_outctrl_gr2 aib_outen2_setting1 hssi_aibcr_tx_aib_outndrv_r12 hssi_aibcr_tx_aib_outndrv_r12 aib_ndrv12_setting1 hssi_aibcr_tx_aib_outndrv_r34 hssi_aibcr_tx_aib_outndrv_r34 aib_ndrv34_setting1 hssi_aibcr_tx_aib_outndrv_r56 hssi_aibcr_tx_aib_outndrv_r56 aib_ndrv56_setting1 hssi_aibcr_tx_aib_outndrv_r78 hssi_aibcr_tx_aib_outndrv_r78 aib_ndrv78_setting1 hssi_aibcr_tx_aib_outpdrv_r12 hssi_aibcr_tx_aib_outpdrv_r12 aib_pdrv12_setting1 hssi_aibcr_tx_aib_outpdrv_r34 hssi_aibcr_tx_aib_outpdrv_r34 aib_pdrv34_setting1 hssi_aibcr_tx_aib_outpdrv_r56 hssi_aibcr_tx_aib_outpdrv_r56 aib_pdrv56_setting1 hssi_aibcr_tx_aib_outpdrv_r78 hssi_aibcr_tx_aib_outpdrv_r78 aib_pdrv78_setting1 hssi_aibcr_tx_aib_red_dirclkn_shiften hssi_aibcr_tx_aib_red_dirclkn_shiften aib_red_dirclkn_shift_disable hssi_aibcr_tx_aib_red_dirclkp_shiften hssi_aibcr_tx_aib_red_dirclkp_shiften aib_red_dirclkp_shift_disable hssi_aibcr_tx_aib_red_drx_shiften hssi_aibcr_tx_aib_red_drx_shiften aib_red_drx_shift_disable hssi_aibcr_tx_aib_red_dtx_shiften hssi_aibcr_tx_aib_red_dtx_shiften aib_red_dtx_shift_disable hssi_aibcr_tx_aib_red_pinp_shiften hssi_aibcr_tx_aib_red_pinp_shiften aib_red_pinp_shift_disable hssi_aibcr_tx_aib_red_rx_shiften hssi_aibcr_tx_aib_red_rx_shiften aib_red_rx_shift_disable hssi_aibcr_tx_aib_red_tx_shiften hssi_aibcr_tx_aib_red_tx_shiften aib_red_tx_shift_disable hssi_aibcr_tx_aib_red_txferclkout_shiften hssi_aibcr_tx_aib_red_txferclkout_shiften aib_red_txferclkout_shift_disable hssi_aibcr_tx_aib_red_txferclkoutn_shiften hssi_aibcr_tx_aib_red_txferclkoutn_shiften aib_red_txferclkoutn_shift_disable hssi_aibcr_tx_dfd_dll_dcc_en hssi_aibcr_tx_dfd_dll_dcc_en disable_dfd hssi_aibcr_tx_dft_hssitestip_dll_dcc_en hssi_aibcr_tx_dft_hssitestip_dll_dcc_en disable_dft hssi_aibcr_tx_op_mode hssi_aibcr_tx_op_mode tx_dll_disable hssi_aibcr_tx_powermode_ac hssi_aibcr_tx_powermode_ac txdatapath_low_speed_pwr hssi_aibcr_tx_powermode_dc hssi_aibcr_tx_powermode_dc powerup hssi_aibcr_tx_redundancy_en hssi_aibcr_tx_redundancy_en disable hssi_aibcr_tx_sup_mode hssi_aibcr_tx_sup_mode user_mode hssi_aibcr_tx_silicon_rev hssi_aibcr_tx_silicon_rev 14nm5bcr2eb hssi_aibnd_rx_aib_ber_margining_ctrl hssi_aibnd_rx_aib_ber_margining_ctrl aib_ber_margining_setting0 hssi_aibnd_rx_aib_datasel_gr0 hssi_aibnd_rx_aib_datasel_gr0 aib_datasel0_setting0 hssi_aibnd_rx_aib_datasel_gr1 hssi_aibnd_rx_aib_datasel_gr1 aib_datasel1_setting1 hssi_aibnd_rx_aib_datasel_gr2 hssi_aibnd_rx_aib_datasel_gr2 aib_datasel2_setting1 hssi_aibnd_rx_aib_dllstr_align_clkdiv hssi_aibnd_rx_aib_dllstr_align_clkdiv aib_dllstr_align_clkdiv_setting1 hssi_aibnd_rx_aib_dllstr_align_dly_pst hssi_aibnd_rx_aib_dllstr_align_dly_pst aib_dllstr_align_dly_pst_setting0 hssi_aibnd_rx_aib_dllstr_align_dy_ctl_static hssi_aibnd_rx_aib_dllstr_align_dy_ctl_static aib_dllstr_align_dy_ctl_static_setting1 hssi_aibnd_rx_aib_dllstr_align_dy_ctlsel hssi_aibnd_rx_aib_dllstr_align_dy_ctlsel aib_dllstr_align_dy_ctlsel_setting1 hssi_aibnd_rx_aib_dllstr_align_entest hssi_aibnd_rx_aib_dllstr_align_entest aib_dllstr_align_test_disable hssi_aibnd_rx_aib_dllstr_align_halfcode hssi_aibnd_rx_aib_dllstr_align_halfcode aib_dllstr_align_halfcode_enable hssi_aibnd_rx_aib_dllstr_align_selflock hssi_aibnd_rx_aib_dllstr_align_selflock aib_dllstr_align_selflock_enable hssi_aibnd_rx_aib_dllstr_align_st_core_dn_prgmnvrt hssi_aibnd_rx_aib_dllstr_align_st_core_dn_prgmnvrt aib_dllstr_align_st_core_dn_prgmnvrt_setting0 hssi_aibnd_rx_aib_dllstr_align_st_core_up_prgmnvrt hssi_aibnd_rx_aib_dllstr_align_st_core_up_prgmnvrt aib_dllstr_align_st_core_up_prgmnvrt_setting0 hssi_aibnd_rx_aib_dllstr_align_st_core_updnen hssi_aibnd_rx_aib_dllstr_align_st_core_updnen aib_dllstr_align_st_core_updnen_setting0 hssi_aibnd_rx_aib_dllstr_align_st_dftmuxsel hssi_aibnd_rx_aib_dllstr_align_st_dftmuxsel aib_dllstr_align_st_dftmuxsel_setting0 hssi_aibnd_rx_aib_dllstr_align_st_en hssi_aibnd_rx_aib_dllstr_align_st_en aib_dllstr_align_st_en_setting1 hssi_aibnd_rx_aib_dllstr_align_st_hps_ctrl_en hssi_aibnd_rx_aib_dllstr_align_st_hps_ctrl_en aib_dllstr_align_hps_ctrl_en_setting0 hssi_aibnd_rx_aib_dllstr_align_st_lockreq_muxsel hssi_aibnd_rx_aib_dllstr_align_st_lockreq_muxsel aib_dllstr_align_st_lockreq_muxsel_setting0 hssi_aibnd_rx_aib_dllstr_align_st_new_dll hssi_aibnd_rx_aib_dllstr_align_st_new_dll aib_dllstr_align_new_dll_setting0 hssi_aibnd_rx_aib_dllstr_align_st_rst hssi_aibnd_rx_aib_dllstr_align_st_rst aib_dllstr_align_st_rst_setting0 hssi_aibnd_rx_aib_dllstr_align_st_rst_prgmnvrt hssi_aibnd_rx_aib_dllstr_align_st_rst_prgmnvrt aib_dllstr_align_st_rst_prgmnvrt_setting0 hssi_aibnd_rx_aib_dllstr_align_test_clk_pll_en_n hssi_aibnd_rx_aib_dllstr_align_test_clk_pll_en_n aib_dllstr_align_test_clk_pll_en_n_disable hssi_aibnd_rx_aib_inctrl_gr0 hssi_aibnd_rx_aib_inctrl_gr0 aib_inctrl0_setting1 hssi_aibnd_rx_aib_inctrl_gr1 hssi_aibnd_rx_aib_inctrl_gr1 aib_inctrl1_setting3 hssi_aibnd_rx_aib_inctrl_gr2 hssi_aibnd_rx_aib_inctrl_gr2 aib_inctrl2_setting2 hssi_aibnd_rx_aib_inctrl_gr3 hssi_aibnd_rx_aib_inctrl_gr3 aib_inctrl3_setting3 hssi_aibnd_rx_aib_outctrl_gr0 hssi_aibnd_rx_aib_outctrl_gr0 aib_outen0_setting1 hssi_aibnd_rx_aib_outctrl_gr1 hssi_aibnd_rx_aib_outctrl_gr1 aib_outen1_setting1 hssi_aibnd_rx_aib_outctrl_gr2 hssi_aibnd_rx_aib_outctrl_gr2 aib_outen2_setting1 hssi_aibnd_rx_aib_outndrv_r12 hssi_aibnd_rx_aib_outndrv_r12 aib_ndrv12_setting1 hssi_aibnd_rx_aib_outndrv_r34 hssi_aibnd_rx_aib_outndrv_r34 aib_ndrv34_setting1 hssi_aibnd_rx_aib_outndrv_r56 hssi_aibnd_rx_aib_outndrv_r56 aib_ndrv56_setting1 hssi_aibnd_rx_aib_outndrv_r78 hssi_aibnd_rx_aib_outndrv_r78 aib_ndrv78_setting1 hssi_aibnd_rx_aib_outpdrv_r12 hssi_aibnd_rx_aib_outpdrv_r12 aib_pdrv12_setting1 hssi_aibnd_rx_aib_outpdrv_r34 hssi_aibnd_rx_aib_outpdrv_r34 aib_pdrv34_setting1 hssi_aibnd_rx_aib_outpdrv_r56 hssi_aibnd_rx_aib_outpdrv_r56 aib_pdrv56_setting1 hssi_aibnd_rx_aib_outpdrv_r78 hssi_aibnd_rx_aib_outpdrv_r78 aib_pdrv78_setting1 hssi_aibnd_rx_aib_red_shift_en hssi_aibnd_rx_aib_red_shift_en aib_red_shift_disable hssi_aibnd_rx_dft_hssitestip_dll_dcc_en hssi_aibnd_rx_dft_hssitestip_dll_dcc_en disable_dft hssi_aibnd_rx_op_mode hssi_aibnd_rx_op_mode rx_dll_disable hssi_aibnd_rx_powerdown_mode hssi_aibnd_rx_powerdown_mode true hssi_aibnd_rx_powermode_ac hssi_aibnd_rx_powermode_ac rxdatapath_low_speed_pwr hssi_aibnd_rx_powermode_dc hssi_aibnd_rx_powermode_dc powerup hssi_aibnd_rx_powermode_freq_hz_aib_hssi_rx_transfer_clk hssi_aibnd_rx_powermode_freq_hz_aib_hssi_rx_transfer_clk 0 hssi_aibnd_rx_redundancy_en hssi_aibnd_rx_redundancy_en disable hssi_aibnd_rx_sup_mode hssi_aibnd_rx_sup_mode user_mode hssi_aibnd_rx_silicon_rev hssi_aibnd_rx_silicon_rev 14nm5bcr2eb hssi_aibnd_tx_aib_datasel_gr0 hssi_aibnd_tx_aib_datasel_gr0 aib_datasel0_setting0 hssi_aibnd_tx_aib_datasel_gr1 hssi_aibnd_tx_aib_datasel_gr1 aib_datasel1_setting0 hssi_aibnd_tx_aib_datasel_gr2 hssi_aibnd_tx_aib_datasel_gr2 aib_datasel2_setting1 hssi_aibnd_tx_aib_datasel_gr3 hssi_aibnd_tx_aib_datasel_gr3 aib_datasel3_setting1 hssi_aibnd_tx_aib_ddrctrl_gr0 hssi_aibnd_tx_aib_ddrctrl_gr0 aib_ddr0_setting1 hssi_aibnd_tx_aib_iinasyncen hssi_aibnd_tx_aib_iinasyncen aib_inasyncen_setting2 hssi_aibnd_tx_aib_iinclken hssi_aibnd_tx_aib_iinclken aib_inclken_setting3 hssi_aibnd_tx_aib_outctrl_gr0 hssi_aibnd_tx_aib_outctrl_gr0 aib_outen0_setting1 hssi_aibnd_tx_aib_outctrl_gr1 hssi_aibnd_tx_aib_outctrl_gr1 aib_outen1_setting1 hssi_aibnd_tx_aib_outctrl_gr2 hssi_aibnd_tx_aib_outctrl_gr2 aib_outen2_setting1 hssi_aibnd_tx_aib_outctrl_gr3 hssi_aibnd_tx_aib_outctrl_gr3 aib_outen3_setting1 hssi_aibnd_tx_aib_outndrv_r34 hssi_aibnd_tx_aib_outndrv_r34 aib_ndrv34_setting1 hssi_aibnd_tx_aib_outndrv_r56 hssi_aibnd_tx_aib_outndrv_r56 aib_ndrv56_setting1 hssi_aibnd_tx_aib_outpdrv_r34 hssi_aibnd_tx_aib_outpdrv_r34 aib_pdrv34_setting1 hssi_aibnd_tx_aib_outpdrv_r56 hssi_aibnd_tx_aib_outpdrv_r56 aib_pdrv56_setting1 hssi_aibnd_tx_aib_red_dirclkn_shiften hssi_aibnd_tx_aib_red_dirclkn_shiften aib_red_dirclkn_shift_disable hssi_aibnd_tx_aib_red_dirclkp_shiften hssi_aibnd_tx_aib_red_dirclkp_shiften aib_red_dirclkp_shift_disable hssi_aibnd_tx_aib_red_drx_shiften hssi_aibnd_tx_aib_red_drx_shiften aib_red_drx_shift_disable hssi_aibnd_tx_aib_red_dtx_shiften hssi_aibnd_tx_aib_red_dtx_shiften aib_red_dtx_shift_disable hssi_aibnd_tx_aib_red_pout_shiften hssi_aibnd_tx_aib_red_pout_shiften aib_red_pout_shift_disable hssi_aibnd_tx_aib_red_rx_shiften hssi_aibnd_tx_aib_red_rx_shiften aib_red_rx_shift_disable hssi_aibnd_tx_aib_red_tx_shiften hssi_aibnd_tx_aib_red_tx_shiften aib_red_tx_shift_disable hssi_aibnd_tx_aib_red_txferclkout_shiften hssi_aibnd_tx_aib_red_txferclkout_shiften aib_red_txferclkout_shift_disable hssi_aibnd_tx_aib_red_txferclkoutn_shiften hssi_aibnd_tx_aib_red_txferclkoutn_shiften aib_red_txferclkoutn_shift_disable hssi_aibnd_tx_aib_tx_clkdiv hssi_aibnd_tx_aib_tx_clkdiv aib_tx_clkdiv_setting1 hssi_aibnd_tx_aib_tx_dcc_byp hssi_aibnd_tx_aib_tx_dcc_byp aib_tx_dcc_byp_enable hssi_aibnd_tx_aib_tx_dcc_byp_iocsr_unused hssi_aibnd_tx_aib_tx_dcc_byp_iocsr_unused aib_tx_dcc_byp_disable_iocsr_unused hssi_aibnd_tx_aib_tx_dcc_cont_cal hssi_aibnd_tx_aib_tx_dcc_cont_cal aib_tx_dcc_cal_cont hssi_aibnd_tx_aib_tx_dcc_cont_cal_iocsr_unused hssi_aibnd_tx_aib_tx_dcc_cont_cal_iocsr_unused aib_tx_dcc_cal_single_iocsr_unused hssi_aibnd_tx_aib_tx_dcc_dft hssi_aibnd_tx_aib_tx_dcc_dft aib_tx_dcc_dft_disable hssi_aibnd_tx_aib_tx_dcc_dft_sel hssi_aibnd_tx_aib_tx_dcc_dft_sel aib_tx_dcc_dft_mode0 hssi_aibnd_tx_aib_tx_dcc_dll_dft_sel hssi_aibnd_tx_aib_tx_dcc_dll_dft_sel aib_tx_dcc_dll_dft_sel_setting0 hssi_aibnd_tx_aib_tx_dcc_dll_entest hssi_aibnd_tx_aib_tx_dcc_dll_entest aib_tx_dcc_dll_test_disable hssi_aibnd_tx_aib_tx_dcc_dy_ctl_static hssi_aibnd_tx_aib_tx_dcc_dy_ctl_static aib_tx_dcc_dy_ctl_static_setting1 hssi_aibnd_tx_aib_tx_dcc_dy_ctlsel hssi_aibnd_tx_aib_tx_dcc_dy_ctlsel aib_tx_dcc_dy_ctlsel_setting0 hssi_aibnd_tx_aib_tx_dcc_en hssi_aibnd_tx_aib_tx_dcc_en aib_tx_dcc_disable hssi_aibnd_tx_aib_tx_dcc_en_iocsr_unused hssi_aibnd_tx_aib_tx_dcc_en_iocsr_unused aib_tx_dcc_disable_iocsr_unused hssi_aibnd_tx_aib_tx_dcc_manual_dn hssi_aibnd_tx_aib_tx_dcc_manual_dn aib_tx_dcc_manual_dn0 hssi_aibnd_tx_aib_tx_dcc_manual_up hssi_aibnd_tx_aib_tx_dcc_manual_up aib_tx_dcc_manual_up0 hssi_aibnd_tx_aib_tx_dcc_rst_prgmnvrt hssi_aibnd_tx_aib_tx_dcc_rst_prgmnvrt aib_tx_dcc_st_rst_prgmnvrt_setting0 hssi_aibnd_tx_aib_tx_dcc_st_core_dn_prgmnvrt hssi_aibnd_tx_aib_tx_dcc_st_core_dn_prgmnvrt aib_tx_dcc_st_core_dn_prgmnvrt_setting0 hssi_aibnd_tx_aib_tx_dcc_st_core_up_prgmnvrt hssi_aibnd_tx_aib_tx_dcc_st_core_up_prgmnvrt aib_tx_dcc_st_core_up_prgmnvrt_setting0 hssi_aibnd_tx_aib_tx_dcc_st_core_updnen hssi_aibnd_tx_aib_tx_dcc_st_core_updnen aib_tx_dcc_st_core_updnen_setting0 hssi_aibnd_tx_aib_tx_dcc_st_dftmuxsel hssi_aibnd_tx_aib_tx_dcc_st_dftmuxsel aib_tx_dcc_st_dftmuxsel_setting0 hssi_aibnd_tx_aib_tx_dcc_st_dly_pst hssi_aibnd_tx_aib_tx_dcc_st_dly_pst aib_tx_dcc_st_dly_pst_setting0 hssi_aibnd_tx_aib_tx_dcc_st_en hssi_aibnd_tx_aib_tx_dcc_st_en aib_tx_dcc_st_en_setting1 hssi_aibnd_tx_aib_tx_dcc_st_hps_ctrl_en hssi_aibnd_tx_aib_tx_dcc_st_hps_ctrl_en aib_tx_dcc_hps_ctrl_en_setting0 hssi_aibnd_tx_aib_tx_dcc_st_lockreq_muxsel hssi_aibnd_tx_aib_tx_dcc_st_lockreq_muxsel aib_tx_dcc_st_lockreq_muxsel_setting0 hssi_aibnd_tx_aib_tx_dcc_st_new_dll hssi_aibnd_tx_aib_tx_dcc_st_new_dll aib_tx_dcc_new_dll_setting0 hssi_aibnd_tx_aib_tx_dcc_st_rst hssi_aibnd_tx_aib_tx_dcc_st_rst aib_tx_dcc_st_rst_setting0 hssi_aibnd_tx_aib_tx_dcc_test_clk_pll_en_n hssi_aibnd_tx_aib_tx_dcc_test_clk_pll_en_n aib_tx_dcc_test_clk_pll_en_n_disable hssi_aibnd_tx_aib_tx_halfcode hssi_aibnd_tx_aib_tx_halfcode aib_tx_halfcode_enable hssi_aibnd_tx_aib_tx_selflock hssi_aibnd_tx_aib_tx_selflock aib_tx_selflock_enable hssi_aibnd_tx_dfd_dll_dcc_en hssi_aibnd_tx_dfd_dll_dcc_en disable_dfd hssi_aibnd_tx_dft_hssitestip_dll_dcc_en hssi_aibnd_tx_dft_hssitestip_dll_dcc_en disable_dft hssi_aibnd_tx_op_mode hssi_aibnd_tx_op_mode tx_dcc_disable hssi_aibnd_tx_powerdown_mode hssi_aibnd_tx_powerdown_mode true hssi_aibnd_tx_powermode_ac hssi_aibnd_tx_powermode_ac txdatapath_low_speed_pwr hssi_aibnd_tx_powermode_dc hssi_aibnd_tx_powermode_dc powerup hssi_aibnd_tx_powermode_freq_hz_aib_hssi_tx_transfer_clk hssi_aibnd_tx_powermode_freq_hz_aib_hssi_tx_transfer_clk 0 hssi_aibnd_tx_redundancy_en hssi_aibnd_tx_redundancy_en disable hssi_aibnd_tx_sup_mode hssi_aibnd_tx_sup_mode user_mode hssi_aibnd_tx_silicon_rev hssi_aibnd_tx_silicon_rev 14nm5bcr2eb hssi_avmm1_if_pcs_arbiter_ctrl hssi_avmm1_if_pcs_arbiter_ctrl avmm1_arbiter_uc_sel hssi_avmm1_if_hssiadapt_avmm_clk_dcg_en hssi_avmm1_if_hssiadapt_avmm_clk_dcg_en disable hssi_avmm1_if_hssiadapt_avmm_clk_scg_en hssi_avmm1_if_hssiadapt_avmm_clk_scg_en disable hssi_avmm1_if_pldadapt_avmm_clk_scg_en hssi_avmm1_if_pldadapt_avmm_clk_scg_en disable hssi_avmm1_if_pcs_cal_done hssi_avmm1_if_pcs_cal_done avmm1_cal_done_deassert hssi_avmm1_if_pcs_cal_reserved hssi_avmm1_if_pcs_cal_reserved 0 hssi_avmm1_if_pcs_calibration_feature_en hssi_avmm1_if_pcs_calibration_feature_en avmm1_pcs_calibration_en hssi_avmm1_if_pldadapt_gate_dis hssi_avmm1_if_pldadapt_gate_dis disable hssi_avmm1_if_pcs_hip_cal_en hssi_avmm1_if_pcs_hip_cal_en disable hssi_avmm1_if_hssiadapt_nfhssi_calibratio_feature_en hssi_avmm1_if_hssiadapt_nfhssi_calibratio_feature_en disable hssi_avmm1_if_pldadapt_nfhssi_calibratio_feature_en hssi_avmm1_if_pldadapt_nfhssi_calibratio_feature_en enable hssi_avmm1_if_hssiadapt_osc_clk_scg_en hssi_avmm1_if_hssiadapt_osc_clk_scg_en disable hssi_avmm1_if_pldadapt_osc_clk_scg_en hssi_avmm1_if_pldadapt_osc_clk_scg_en disable hssi_avmm1_if_hssiadapt_read_blocking_enable hssi_avmm1_if_hssiadapt_read_blocking_enable enable hssi_avmm1_if_pldadapt_read_blocking_enable hssi_avmm1_if_pldadapt_read_blocking_enable enable hssi_avmm1_if_hssiadapt_uc_blocking_enable hssi_avmm1_if_hssiadapt_uc_blocking_enable enable hssi_avmm1_if_pldadapt_uc_blocking_enable hssi_avmm1_if_pldadapt_uc_blocking_enable enable hssi_avmm1_if_hssiadapt_write_resp_en hssi_avmm1_if_hssiadapt_write_resp_en disable hssi_avmm1_if_hssiadapt_avmm_osc_clock_setting hssi_avmm1_if_hssiadapt_avmm_osc_clock_setting osc_clk_div_by1 hssi_avmm1_if_pldadapt_avmm_osc_clock_setting hssi_avmm1_if_pldadapt_avmm_osc_clock_setting osc_clk_div_by1 hssi_avmm1_if_hssiadapt_avmm_testbus_sel hssi_avmm1_if_hssiadapt_avmm_testbus_sel avmm1_transfer_testbus hssi_avmm1_if_pldadapt_avmm_testbus_sel hssi_avmm1_if_pldadapt_avmm_testbus_sel avmm1_transfer_testbus hssi_avmm1_if_func_mode hssi_avmm1_if_func_mode c3adpt_pmadir hssi_avmm1_if_hssiadapt_sr_hip_mode hssi_avmm1_if_hssiadapt_sr_hip_mode disable_hip hssi_avmm1_if_hssiadapt_hip_mode hssi_avmm1_if_hssiadapt_hip_mode disable_hip hssi_avmm1_if_pldadapt_hip_mode hssi_avmm1_if_pldadapt_hip_mode disable_hip hssi_avmm1_if_hssiadapt_sr_powerdown_mode hssi_avmm1_if_hssiadapt_sr_powerdown_mode powerup hssi_avmm1_if_hssiadapt_sr_sr_free_run_div_clk hssi_avmm1_if_hssiadapt_sr_sr_free_run_div_clk out_of_reset_sync hssi_avmm1_if_hssiadapt_sr_sr_hip_en hssi_avmm1_if_hssiadapt_sr_sr_hip_en disable hssi_avmm1_if_hssiadapt_sr_sr_osc_clk_div_sel hssi_avmm1_if_hssiadapt_sr_sr_osc_clk_div_sel non_div hssi_avmm1_if_hssiadapt_sr_sr_osc_clk_scg_en hssi_avmm1_if_hssiadapt_sr_sr_osc_clk_scg_en disable hssi_avmm1_if_hssiadapt_sr_sr_parity_en hssi_avmm1_if_hssiadapt_sr_sr_parity_en disable hssi_avmm1_if_hssiadapt_sr_sr_reserved_in_en hssi_avmm1_if_hssiadapt_sr_sr_reserved_in_en enable hssi_avmm1_if_hssiadapt_sr_sr_reserved_out_en hssi_avmm1_if_hssiadapt_sr_sr_reserved_out_en enable hssi_avmm1_if_hssiadapt_sr_sup_mode hssi_avmm1_if_hssiadapt_sr_sup_mode user_mode hssi_avmm1_if_topology hssi_avmm1_if_topology disabled_block hssi_avmm1_if_silicon_rev hssi_avmm1_if_silicon_rev 14nm5bcr2eb hssi_avmm1_if_calibration_type hssi_avmm1_if_calibration_type one_time hssi_common_pcs_pma_interface_asn_clk_enable hssi_common_pcs_pma_interface_asn_clk_enable false hssi_common_pcs_pma_interface_asn_enable hssi_common_pcs_pma_interface_asn_enable dis_asn hssi_common_pcs_pma_interface_block_sel hssi_common_pcs_pma_interface_block_sel eight_g_pcs hssi_common_pcs_pma_interface_bypass_early_eios hssi_common_pcs_pma_interface_bypass_early_eios true hssi_common_pcs_pma_interface_bypass_pcie_switch hssi_common_pcs_pma_interface_bypass_pcie_switch true hssi_common_pcs_pma_interface_bypass_pma_ltr hssi_common_pcs_pma_interface_bypass_pma_ltr true hssi_common_pcs_pma_interface_bypass_pma_sw_done hssi_common_pcs_pma_interface_bypass_pma_sw_done false hssi_common_pcs_pma_interface_bypass_ppm_lock hssi_common_pcs_pma_interface_bypass_ppm_lock false hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp true hssi_common_pcs_pma_interface_bypass_txdetectrx hssi_common_pcs_pma_interface_bypass_txdetectrx true hssi_common_pcs_pma_interface_cdr_control hssi_common_pcs_pma_interface_cdr_control dis_cdr_ctrl hssi_common_pcs_pma_interface_cid_enable hssi_common_pcs_pma_interface_cid_enable dis_cid_mode hssi_common_pcs_pma_interface_cp_cons_sel hssi_common_pcs_pma_interface_cp_cons_sel cp_cons_master hssi_common_pcs_pma_interface_cp_dwn_mstr hssi_common_pcs_pma_interface_cp_dwn_mstr true hssi_common_pcs_pma_interface_cp_up_mstr hssi_common_pcs_pma_interface_cp_up_mstr true hssi_common_pcs_pma_interface_ctrl_plane_bonding hssi_common_pcs_pma_interface_ctrl_plane_bonding individual hssi_common_pcs_pma_interface_data_mask_count hssi_common_pcs_pma_interface_data_mask_count 0 hssi_common_pcs_pma_interface_data_mask_count_multi hssi_common_pcs_pma_interface_data_mask_count_multi 0 hssi_common_pcs_pma_interface_dft_observation_clock_selection hssi_common_pcs_pma_interface_dft_observation_clock_selection dft_clk_obsrv_tx0 hssi_common_pcs_pma_interface_early_eios_counter hssi_common_pcs_pma_interface_early_eios_counter 0 hssi_common_pcs_pma_interface_force_freqdet hssi_common_pcs_pma_interface_force_freqdet force_freqdet_dis hssi_common_pcs_pma_interface_free_run_clk_enable hssi_common_pcs_pma_interface_free_run_clk_enable false hssi_common_pcs_pma_interface_ignore_sigdet_g23 hssi_common_pcs_pma_interface_ignore_sigdet_g23 false hssi_common_pcs_pma_interface_pc_en_counter hssi_common_pcs_pma_interface_pc_en_counter 0 hssi_common_pcs_pma_interface_pc_rst_counter hssi_common_pcs_pma_interface_pc_rst_counter 0 hssi_common_pcs_pma_interface_pcie_hip_mode hssi_common_pcs_pma_interface_pcie_hip_mode hip_disable hssi_common_pcs_pma_interface_ph_fifo_reg_mode hssi_common_pcs_pma_interface_ph_fifo_reg_mode phfifo_reg_mode_dis hssi_common_pcs_pma_interface_phfifo_flush_wait hssi_common_pcs_pma_interface_phfifo_flush_wait 0 hssi_common_pcs_pma_interface_pipe_if_g3pcs hssi_common_pcs_pma_interface_pipe_if_g3pcs pipe_if_8gpcs hssi_common_pcs_pma_interface_pma_done_counter hssi_common_pcs_pma_interface_pma_done_counter 0 hssi_common_pcs_pma_interface_pma_if_dft_en hssi_common_pcs_pma_interface_pma_if_dft_en dft_dis hssi_common_pcs_pma_interface_pma_if_dft_val hssi_common_pcs_pma_interface_pma_if_dft_val dft_0 hssi_common_pcs_pma_interface_ppm_cnt_rst hssi_common_pcs_pma_interface_ppm_cnt_rst ppm_cnt_rst_dis hssi_common_pcs_pma_interface_ppm_deassert_early hssi_common_pcs_pma_interface_ppm_deassert_early deassert_early_dis hssi_common_pcs_pma_interface_ppm_det_buckets hssi_common_pcs_pma_interface_ppm_det_buckets ppm_300_100_bucket hssi_common_pcs_pma_interface_ppm_gen1_2_cnt hssi_common_pcs_pma_interface_ppm_gen1_2_cnt cnt_32k hssi_common_pcs_pma_interface_ppm_post_eidle_delay hssi_common_pcs_pma_interface_ppm_post_eidle_delay cnt_200_cycles hssi_common_pcs_pma_interface_ppmsel hssi_common_pcs_pma_interface_ppmsel ppmsel_1000 hssi_common_pcs_pma_interface_prot_mode hssi_common_pcs_pma_interface_prot_mode other_protocols hssi_common_pcs_pma_interface_rxvalid_mask hssi_common_pcs_pma_interface_rxvalid_mask rxvalid_mask_dis hssi_common_pcs_pma_interface_sigdet_wait_counter hssi_common_pcs_pma_interface_sigdet_wait_counter 0 hssi_common_pcs_pma_interface_sigdet_wait_counter_multi hssi_common_pcs_pma_interface_sigdet_wait_counter_multi 0 hssi_common_pcs_pma_interface_sim_mode hssi_common_pcs_pma_interface_sim_mode disable hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en false hssi_common_pcs_pma_interface_sup_mode hssi_common_pcs_pma_interface_sup_mode user_mode hssi_common_pcs_pma_interface_testout_sel hssi_common_pcs_pma_interface_testout_sel ppm_det_test hssi_common_pcs_pma_interface_wait_clk_on_off_timer hssi_common_pcs_pma_interface_wait_clk_on_off_timer 0 hssi_common_pcs_pma_interface_wait_pipe_synchronizing hssi_common_pcs_pma_interface_wait_pipe_synchronizing 0 hssi_common_pcs_pma_interface_wait_send_syncp_fbkp hssi_common_pcs_pma_interface_wait_send_syncp_fbkp 0 hssi_common_pcs_pma_interface_silicon_rev hssi_common_pcs_pma_interface_silicon_rev 14nm5bcr2eb hssi_common_pcs_pma_interface_reconfig_settings hssi_common_pcs_pma_interface_reconfig_settings {} hssi_common_pld_pcs_interface_dft_clk_out_en hssi_common_pld_pcs_interface_dft_clk_out_en dft_clk_out_disable hssi_common_pld_pcs_interface_dft_clk_out_sel hssi_common_pld_pcs_interface_dft_clk_out_sel teng_rx_dft_clk hssi_common_pld_pcs_interface_hrdrstctrl_en hssi_common_pld_pcs_interface_hrdrstctrl_en hrst_dis hssi_common_pld_pcs_interface_pcs_testbus_block_sel hssi_common_pld_pcs_interface_pcs_testbus_block_sel pma_if hssi_common_pld_pcs_interface_silicon_rev hssi_common_pld_pcs_interface_silicon_rev 14nm5bcr2eb hssi_common_pld_pcs_interface_reconfig_settings hssi_common_pld_pcs_interface_reconfig_settings {} pma_adapt_sequencer_rx_path_rstn_overrideb pma_adapt_sequencer_rx_path_rstn_overrideb use_sequencer pma_adapt_sequencer_silicon_rev pma_adapt_sequencer_silicon_rev 14nm5bcr2eb pma_pcie_gen_switch_rx_path_pcie_gen_switch_en pma_pcie_gen_switch_rx_path_pcie_gen_switch_en bypass_pcie_switch pma_pcie_gen_switch_rx_pci_switch_dly pma_pcie_gen_switch_rx_pci_switch_dly 0 pma_pcie_gen_switch_silicon_rev pma_pcie_gen_switch_silicon_rev 14nm5bcr2eb pma_adapt_adapt_mode pma_adapt_adapt_mode manual pma_adapt_adp_ac_ctle_cal_win pma_adapt_adp_ac_ctle_cal_win radp_ac_ctle_cal_win_4 pma_adapt_adp_ac_ctle_cocurrent_mode_sel pma_adapt_adp_ac_ctle_cocurrent_mode_sel radp_ac_ctle_cocurrent_mode_sel_mode_1 pma_adapt_adp_ac_ctle_en pma_adapt_adp_ac_ctle_en radp_ac_ctle_en_disable pma_adapt_adp_ac_ctle_hold_en pma_adapt_adp_ac_ctle_hold_en radp_ac_ctle_hold_en_not_hold pma_adapt_adp_ac_ctle_initial_load pma_adapt_adp_ac_ctle_initial_load radp_ac_ctle_initial_load_0 pma_adapt_adp_ac_ctle_initial_value pma_adapt_adp_ac_ctle_initial_value radp_ac_ctle_initial_value_8 pma_adapt_adp_ac_ctle_mode_sel pma_adapt_adp_ac_ctle_mode_sel radp_ac_ctle_mode_sel_concurrent pma_adapt_adp_ac_ctle_ph1_win pma_adapt_adp_ac_ctle_ph1_win radp_ac_ctle_ph1_win_2p19 pma_adapt_adp_adapt_control_sel pma_adapt_adp_adapt_control_sel radp_adapt_control_sel_from_cram pma_adapt_adp_adapt_start pma_adapt_adp_adapt_start radp_adapt_start_0 pma_adapt_adp_bist_datapath_en pma_adapt_adp_bist_datapath_en radp_bist_datapath_en_disable pma_adapt_adp_bist_errcount_rstn pma_adapt_adp_bist_errcount_rstn radp_bist_errcount_rstn_0 pma_adapt_adp_bist_mode_sel pma_adapt_adp_bist_mode_sel radp_bist_mode_sel_prbs31 pma_adapt_adp_clkgate_enb pma_adapt_adp_clkgate_enb radp_clkgate_enb_disable pma_adapt_adp_clkout_div_sel pma_adapt_adp_clkout_div_sel radp_clkout_div_sel_div2_4cycle pma_adapt_adp_ctle_bypass_ac pma_adapt_adp_ctle_bypass_ac radp_ctle_bypass_ac_bypass pma_adapt_adp_ctle_bypass_dc pma_adapt_adp_ctle_bypass_dc radp_ctle_bypass_dc_bypass pma_adapt_adp_dc_ctle_accum_depth pma_adapt_adp_dc_ctle_accum_depth 8 pma_adapt_adp_dc_ctle_en pma_adapt_adp_dc_ctle_en radp_dc_ctle_en_disable pma_adapt_adp_dc_ctle_hold_en pma_adapt_adp_dc_ctle_hold_en radp_dc_ctle_hold_en_not_hold pma_adapt_adp_dc_ctle_initial_load pma_adapt_adp_dc_ctle_initial_load radp_dc_ctle_initial_load_0 pma_adapt_adp_dc_ctle_initial_value pma_adapt_adp_dc_ctle_initial_value radp_dc_ctle_initial_value_16 pma_adapt_adp_dc_ctle_mode0_win_size pma_adapt_adp_dc_ctle_mode0_win_size radp_dc_ctle_mode0_win_size_4_taps pma_adapt_adp_dc_ctle_mode0_win_start pma_adapt_adp_dc_ctle_mode0_win_start 0 pma_adapt_adp_dc_ctle_mode1_h1_ratio pma_adapt_adp_dc_ctle_mode1_h1_ratio 8 pma_adapt_adp_dc_ctle_mode2_h2_limit pma_adapt_adp_dc_ctle_mode2_h2_limit 7 pma_adapt_adp_dc_ctle_mode_sel pma_adapt_adp_dc_ctle_mode_sel radp_dc_ctle_mode_sel_mode_2 pma_adapt_adp_dc_ctle_onetime pma_adapt_adp_dc_ctle_onetime radp_dc_ctle_onetime_disable pma_adapt_adp_dc_ctle_onetime_threshold pma_adapt_adp_dc_ctle_onetime_threshold radp_dc_ctle_onetime_threshold_256 pma_adapt_adp_dfe_accum_depth pma_adapt_adp_dfe_accum_depth 8 pma_adapt_adp_dfe_en pma_adapt_adp_dfe_en radp_dfe_en_disable pma_adapt_adp_dfe_fxtap_bypass pma_adapt_adp_dfe_fxtap_bypass radp_dfe_fxtap_bypass_bypass pma_adapt_adp_dfe_hold_en pma_adapt_adp_dfe_hold_en radp_dfe_hold_en_not_hold pma_adapt_adp_dfe_hold_sel pma_adapt_adp_dfe_hold_sel radp_dfe_hold_sel_no pma_adapt_adp_dfe_onetime pma_adapt_adp_dfe_onetime radp_dfe_onetime_disable pma_adapt_adp_dfe_onetime_threshold pma_adapt_adp_dfe_onetime_threshold radp_dfe_onetime_threshold_2048 pma_adapt_adp_dfe_tap1_initial_load pma_adapt_adp_dfe_tap1_initial_load radp_dfe_tap1_initial_load_0 pma_adapt_adp_dfe_tap1_initial_value pma_adapt_adp_dfe_tap1_initial_value radp_dfe_tap1_initial_value_0 pma_adapt_adp_dfe_tap_sel_en pma_adapt_adp_dfe_tap_sel_en radp_dfe_tap_sel_en_no pma_adapt_adp_dlev_accum_depth pma_adapt_adp_dlev_accum_depth 6 pma_adapt_adp_dlev_bypass pma_adapt_adp_dlev_bypass radp_dlev_bypass_bypass pma_adapt_adp_dlev_en pma_adapt_adp_dlev_en radp_dlev_en_disable pma_adapt_adp_dlev_hold_en pma_adapt_adp_dlev_hold_en radp_dlev_hold_en_not_hold pma_adapt_adp_dlev_initial_load pma_adapt_adp_dlev_initial_load radp_dlev_initial_load_0 pma_adapt_adp_dlev_initial_value pma_adapt_adp_dlev_initial_value radp_dlev_initial_value_38 pma_adapt_adp_dlev_onetime pma_adapt_adp_dlev_onetime radp_dlev_onetime_disable pma_adapt_adp_dlev_onetime_threshold pma_adapt_adp_dlev_onetime_threshold radp_dlev_onetime_threshold_4096 pma_adapt_adp_dlev_sel pma_adapt_adp_dlev_sel radp_dlev_sel_mux pma_adapt_adp_force_freqlock pma_adapt_adp_force_freqlock radp_force_freqlock_use pma_adapt_adp_frame_capture pma_adapt_adp_frame_capture radp_frame_capture_0 pma_adapt_adp_frame_en pma_adapt_adp_frame_en radp_frame_en_disable pma_adapt_adp_frame_odi_sel pma_adapt_adp_frame_odi_sel radp_frame_odi_sel_deser_err pma_adapt_adp_frame_out_sel pma_adapt_adp_frame_out_sel radp_frame_out_sel_select_a pma_adapt_adp_load_sig_sel pma_adapt_adp_load_sig_sel radp_load_sig_sel_from_interanl pma_adapt_adp_oc_accum_depth pma_adapt_adp_oc_accum_depth 11 pma_adapt_adp_oc_bypass pma_adapt_adp_oc_bypass radp_oc_bypass_bypass pma_adapt_adp_oc_en pma_adapt_adp_oc_en radp_oc_en_disable pma_adapt_adp_oc_hold_en pma_adapt_adp_oc_hold_en radp_oc_hold_en_not_hold pma_adapt_adp_oc_initial_load pma_adapt_adp_oc_initial_load radp_oc_initial_load_0 pma_adapt_adp_oc_initial_sign pma_adapt_adp_oc_initial_sign radp_oc_initial_sign_0 pma_adapt_adp_oc_initial_value pma_adapt_adp_oc_initial_value 0 pma_adapt_adp_oc_onetime pma_adapt_adp_oc_onetime radp_oc_onetime_disable pma_adapt_adp_oc_onetime_threshold pma_adapt_adp_oc_onetime_threshold radp_oc_onetime_threshold_1024 pma_adapt_adp_odi_bit_sel pma_adapt_adp_odi_bit_sel radp_odi_bit_sel_all_bits pma_adapt_adp_odi_control_sel pma_adapt_adp_odi_control_sel radp_odi_control_sel_from_cram pma_adapt_adp_odi_count_threshold pma_adapt_adp_odi_count_threshold radp_odi_count_threshold_1e6 pma_adapt_adp_odi_dfe_spec_en pma_adapt_adp_odi_dfe_spec_en radp_odi_dfe_spec_en_enable pma_adapt_adp_odi_dlev_sel pma_adapt_adp_odi_dlev_sel radp_odi_dlev_sel_0 pma_adapt_adp_odi_en pma_adapt_adp_odi_en radp_odi_en_disable pma_adapt_adp_odi_mode pma_adapt_adp_odi_mode radp_odi_mode_detect_errdata pma_adapt_adp_odi_rstn pma_adapt_adp_odi_rstn radp_odi_rstn_1 pma_adapt_adp_odi_spec_sel pma_adapt_adp_odi_spec_sel radp_odi_spec_sel_0 pma_adapt_adp_odi_start pma_adapt_adp_odi_start radp_odi_start_0 pma_adapt_adp_pat_dlev_sign_avg_win pma_adapt_adp_pat_dlev_sign_avg_win radp_pat_dlev_sign_avg_win_2x pma_adapt_adp_pat_dlev_sign_force pma_adapt_adp_pat_dlev_sign_force radp_pat_dlev_sign_force_determined_by_cram pma_adapt_adp_pat_dlev_sign_value pma_adapt_adp_pat_dlev_sign_value radp_pat_dlev_sign_value_1 pma_adapt_adp_pat_spec_sign_avg_win pma_adapt_adp_pat_spec_sign_avg_win radp_pat_spec_sign_avg_win_256 pma_adapt_adp_pat_spec_sign_force pma_adapt_adp_pat_spec_sign_force radp_pat_spec_sign_force_generated_internally pma_adapt_adp_pat_spec_sign_value pma_adapt_adp_pat_spec_sign_value radp_pat_spec_sign_value_0 pma_adapt_adp_pat_trans_filter pma_adapt_adp_pat_trans_filter radp_pat_trans_filter_5 pma_adapt_adp_pat_trans_only_en pma_adapt_adp_pat_trans_only_en radp_pat_trans_only_en_enable pma_adapt_adp_pcie_adp_bypass pma_adapt_adp_pcie_adp_bypass radp_pcie_adp_bypass_no pma_adapt_adp_pcie_eqz pma_adapt_adp_pcie_eqz radp_pcie_eqz_non_pcie_mode pma_adapt_adp_pcie_hold_sel pma_adapt_adp_pcie_hold_sel 0 pma_adapt_adp_pcs_option pma_adapt_adp_pcs_option radp_pcs_option_0 pma_adapt_adp_po_actslp_ratio pma_adapt_adp_po_actslp_ratio radp_po_actslp_ratio_10_percent pma_adapt_adp_po_en pma_adapt_adp_po_en radp_po_en_disable pma_adapt_adp_po_gb_act2slp pma_adapt_adp_po_gb_act2slp radp_po_gb_act2slp_288ns pma_adapt_adp_po_gb_slp2act pma_adapt_adp_po_gb_slp2act radp_po_gb_slp2act_288ns pma_adapt_adp_po_initwait pma_adapt_adp_po_initwait radp_po_initwait_10sec pma_adapt_adp_po_sleep_win pma_adapt_adp_po_sleep_win radp_po_sleep_win_2_sec pma_adapt_adp_po_startpos pma_adapt_adp_po_startpos radp_po_startpos_6ov7 pma_adapt_adp_reserved pma_adapt_adp_reserved 0 pma_adapt_adp_rstn pma_adapt_adp_rstn radp_rstn_1 pma_adapt_adp_status_sel pma_adapt_adp_status_sel radp_status_sel_0 pma_adapt_adp_tx_accum_depth pma_adapt_adp_tx_accum_depth 4 pma_adapt_adp_tx_adp_accumulate pma_adapt_adp_tx_adp_accumulate radp_tx_adp_accumulate_0 pma_adapt_adp_tx_adp_en pma_adapt_adp_tx_adp_en radp_tx_adp_en_0 pma_adapt_adp_tx_up_dn_flip pma_adapt_adp_tx_up_dn_flip radp_tx_up_dn_flip_0 pma_adapt_adp_vga_accum_depth pma_adapt_adp_vga_accum_depth 9 pma_adapt_adp_vga_bypass pma_adapt_adp_vga_bypass radp_vga_bypass_bypass pma_adapt_adp_vga_ctle_low_limit pma_adapt_adp_vga_ctle_low_limit radp_vga_ctle_low_limit_0 pma_adapt_adp_vga_dlev_offset pma_adapt_adp_vga_dlev_offset 4 pma_adapt_adp_vga_dlev_target pma_adapt_adp_vga_dlev_target 15 pma_adapt_adp_vga_en pma_adapt_adp_vga_en radp_vga_en_disable pma_adapt_adp_vga_hold_en pma_adapt_adp_vga_hold_en radp_vga_hold_en_not_hold pma_adapt_adp_vga_initial_load pma_adapt_adp_vga_initial_load radp_vga_initial_load_0 pma_adapt_adp_vga_initial_value pma_adapt_adp_vga_initial_value radp_vga_initial_value_4 pma_adapt_adp_vga_onetime pma_adapt_adp_vga_onetime radp_vga_onetime_disable pma_adapt_adp_vga_onetime_threshold pma_adapt_adp_vga_onetime_threshold radp_vga_onetime_threshold_512 pma_adapt_advanced_mode pma_adapt_advanced_mode false pma_adapt_datarate_bps pma_adapt_datarate_bps 10312500000 pma_adapt_initial_settings pma_adapt_initial_settings true pma_adapt_odi_mode pma_adapt_odi_mode odi_disable pma_adapt_offset_mode pma_adapt_offset_mode offset_disable pma_adapt_optimal pma_adapt_optimal true pma_adapt_power_mode pma_adapt_power_mode powsav_disable pma_adapt_powermode_ac_adaptation pma_adapt_powermode_ac_adaptation adapt_ac_off pma_adapt_powermode_ac_deser_adapt pma_adapt_powermode_ac_deser_adapt adapt_deser_ac_off pma_adapt_powermode_ac_dfe_adapt pma_adapt_powermode_ac_dfe_adapt adapt_dfe_ac_off pma_adapt_powermode_dc_adaptation pma_adapt_powermode_dc_adaptation powerdown_adapt pma_adapt_powermode_dc_deser_adapt pma_adapt_powermode_dc_deser_adapt powerdown_adapt_deser pma_adapt_powermode_dc_dfe_adapt pma_adapt_powermode_dc_dfe_adapt powerdown_adapt_dfe pma_adapt_prot_mode pma_adapt_prot_mode basic_rx pma_adapt_sup_mode pma_adapt_sup_mode user_mode pma_adapt_silicon_rev pma_adapt_silicon_rev 14nm5bcr2eb cdr_pll_analog_mode cdr_pll_analog_mode user_custom cdr_pll_atb_select_control cdr_pll_atb_select_control atb_off cdr_pll_auto_reset_on cdr_pll_auto_reset_on auto_reset_off cdr_pll_bandwidth_range_high cdr_pll_bandwidth_range_high 1 cdr_pll_bandwidth_range_low cdr_pll_bandwidth_range_low 1 cdr_pll_bbpd_data_pattern_filter_select cdr_pll_bbpd_data_pattern_filter_select bbpd_data_pat_off cdr_pll_bti_protected cdr_pll_bti_protected false cdr_pll_bw_mode cdr_pll_bw_mode mid_bw cdr_pll_bypass_a_edge cdr_pll_bypass_a_edge bypass_a_edge_off cdr_pll_cal_vco_count_length cdr_pll_cal_vco_count_length sel_8b_count cdr_pll_pm_cr2_rx_path_cdr_clock_enable cdr_pll_pm_cr2_rx_path_cdr_clock_enable cdr_clock_disable cdr_pll_cdr_d2a_enb cdr_pll_cdr_d2a_enb bti_d2a_disable cdr_pll_cdr_odi_select cdr_pll_cdr_odi_select sel_cdr cdr_pll_cdr_phaselock_mode cdr_pll_cdr_phaselock_mode no_ignore_lock cdr_pll_cdr_powerdown_mode cdr_pll_cdr_powerdown_mode power_up cdr_pll_chgpmp_current_dn_pd cdr_pll_chgpmp_current_dn_pd cp_current_pd_dn_setting3 cdr_pll_chgpmp_current_dn_trim cdr_pll_chgpmp_current_dn_trim cp_current_trimming_dn_setting0 cdr_pll_chgpmp_current_pfd cdr_pll_chgpmp_current_pfd cp_current_pfd_setting2 cdr_pll_chgpmp_current_up_pd cdr_pll_chgpmp_current_up_pd cp_current_pd_up_setting3 cdr_pll_chgpmp_current_up_trim cdr_pll_chgpmp_current_up_trim cp_current_trimming_up_setting0 cdr_pll_chgpmp_dn_pd_trim_double cdr_pll_chgpmp_dn_pd_trim_double normal_dn_trim_current cdr_pll_chgpmp_replicate cdr_pll_chgpmp_replicate disable_replica_bias_ctrl cdr_pll_chgpmp_testmode cdr_pll_chgpmp_testmode cp_test_disable cdr_pll_chgpmp_up_pd_trim_double cdr_pll_chgpmp_up_pd_trim_double normal_up_trim_current cdr_pll_chgpmp_vccreg cdr_pll_chgpmp_vccreg vreg_fw0 cdr_pll_clk0_dfe_tfall_adj cdr_pll_clk0_dfe_tfall_adj clk0_dfe_tf0 cdr_pll_clk0_dfe_trise_adj cdr_pll_clk0_dfe_trise_adj clk0_dfe_tr0 cdr_pll_clk180_dfe_tfall_adj cdr_pll_clk180_dfe_tfall_adj clk180_dfe_tf0 cdr_pll_clk180_dfe_trise_adj cdr_pll_clk180_dfe_trise_adj clk180_dfe_tr0 cdr_pll_clk270_dfe_tfall_adj cdr_pll_clk270_dfe_tfall_adj clk270_dfe_tf0 cdr_pll_clk270_dfe_trise_adj cdr_pll_clk270_dfe_trise_adj clk270_dfe_tr0 cdr_pll_clk90_dfe_tfall_adj cdr_pll_clk90_dfe_tfall_adj clk90_dfe_tf0 cdr_pll_clk90_dfe_trise_adj cdr_pll_clk90_dfe_trise_adj clk90_dfe_tr0 cdr_pll_clklow_mux_select cdr_pll_clklow_mux_select clklow_mux_cdr_fbclk cdr_pll_datarate_bps cdr_pll_datarate_bps 10312500000 cdr_pll_diag_loopback_enable cdr_pll_diag_loopback_enable no_diag_rev_loopback cdr_pll_disable_up_dn cdr_pll_disable_up_dn normal_mode cdr_pll_enable_idle_rx_channel_support cdr_pll_enable_idle_rx_channel_support false cdr_pll_f_max_cmu_out_freq cdr_pll_f_max_cmu_out_freq 1 cdr_pll_f_max_m_counter cdr_pll_f_max_m_counter 1 cdr_pll_f_max_pfd cdr_pll_f_max_pfd 350000000 cdr_pll_f_max_ref cdr_pll_f_max_ref 800000000 cdr_pll_f_max_vco cdr_pll_f_max_vco 14150000000 cdr_pll_f_min_gt_channel cdr_pll_f_min_gt_channel 8700000000 cdr_pll_f_min_pfd cdr_pll_f_min_pfd 25000000 cdr_pll_f_min_ref cdr_pll_f_min_ref 25000000 cdr_pll_f_min_vco cdr_pll_f_min_vco 7000000000 cdr_pll_fref_clklow_div cdr_pll_fref_clklow_div 2 cdr_pll_fref_mux_select cdr_pll_fref_mux_select fref_mux_cdr_refclk cdr_pll_gpon_lck2ref_control cdr_pll_gpon_lck2ref_control gpon_lck2ref_off cdr_pll_initial_settings cdr_pll_initial_settings true cdr_pll_lck2ref_delay_control cdr_pll_lck2ref_delay_control lck2ref_delay_2 cdr_pll_lf_resistor_pd cdr_pll_lf_resistor_pd lf_pd_setting3 cdr_pll_lf_resistor_pfd cdr_pll_lf_resistor_pfd lf_pfd_setting2 cdr_pll_lf_ripple_cap cdr_pll_lf_ripple_cap lf_no_ripple cdr_pll_loop_filter_bias_select cdr_pll_loop_filter_bias_select lpflt_bias_7 cdr_pll_loopback_mode cdr_pll_loopback_mode loopback_disabled cdr_pll_lpd_counter cdr_pll_lpd_counter 2 cdr_pll_lpfd_counter cdr_pll_lpfd_counter 2 cdr_pll_ltd_ltr_micro_controller_select cdr_pll_ltd_ltr_micro_controller_select ltd_ltr_pcs cdr_pll_mcnt_div cdr_pll_mcnt_div 16 cdr_pll_n_counter cdr_pll_n_counter 2 cdr_pll_ncnt_div cdr_pll_ncnt_div 2 cdr_pll_optimal cdr_pll_optimal true cdr_pll_out_freq cdr_pll_out_freq 5156250000 cdr_pll_pcie_gen cdr_pll_pcie_gen non_pcie cdr_pll_pd_fastlock_mode cdr_pll_pd_fastlock_mode fast_lock_disable cdr_pll_pd_l_counter cdr_pll_pd_l_counter 2 cdr_pll_pfd_l_counter cdr_pll_pfd_l_counter 2 cdr_pll_position cdr_pll_position position0 cdr_pll_power_mode cdr_pll_power_mode mid_power cdr_pll_powermode_ac_bbpd cdr_pll_powermode_ac_bbpd bbpd_ac_on cdr_pll_powermode_ac_rvcotop cdr_pll_powermode_ac_rvcotop rvcotop_ac_div2 cdr_pll_powermode_ac_txpll cdr_pll_powermode_ac_txpll txpll_ac_off cdr_pll_powermode_dc_bbpd cdr_pll_powermode_dc_bbpd bbpd_dc_on cdr_pll_powermode_dc_rvcotop cdr_pll_powermode_dc_rvcotop rvcotop_dc_div2 cdr_pll_powermode_dc_txpll cdr_pll_powermode_dc_txpll powerdown_txpll cdr_pll_primary_use cdr_pll_primary_use cdr cdr_pll_prot_mode cdr_pll_prot_mode basic_rx cdr_pll_reference_clock_frequency cdr_pll_reference_clock_frequency 644531250 cdr_pll_requires_gt_capable_channel cdr_pll_requires_gt_capable_channel false cdr_pll_reverse_serial_loopback cdr_pll_reverse_serial_loopback no_loopback cdr_pll_rx_pin_as_refclk_mode cdr_pll_rx_pin_as_refclk_mode false cdr_pll_set_cdr_input_freq_range cdr_pll_set_cdr_input_freq_range 149 cdr_pll_set_cdr_v2i_enable cdr_pll_set_cdr_v2i_enable enable_v2i_bias cdr_pll_set_cdr_vco_reset cdr_pll_set_cdr_vco_reset vco_normal cdr_pll_set_cdr_vco_speed cdr_pll_set_cdr_vco_speed 2 cdr_pll_set_cdr_vco_speed_fix cdr_pll_set_cdr_vco_speed_fix 92 cdr_pll_set_cdr_vco_speed_pciegen3 cdr_pll_set_cdr_vco_speed_pciegen3 cdr_vco_max_speedbin_pciegen3 cdr_pll_side cdr_pll_side side_off cdr_pll_speed_grade cdr_pll_speed_grade e2 cdr_pll_sup_mode cdr_pll_sup_mode user_mode cdr_pll_top_or_bottom cdr_pll_top_or_bottom top_or_bot_off cdr_pll_tx_pll_prot_mode cdr_pll_tx_pll_prot_mode txpll_unused cdr_pll_txpll_hclk_driver_enable cdr_pll_txpll_hclk_driver_enable hclk_off cdr_pll_rstb cdr_pll_rstb cdr_lf_reset_off cdr_pll_pm_cr2_tx_rx_uc_dyn_reconfig cdr_pll_pm_cr2_tx_rx_uc_dyn_reconfig uc_dyn_reconfig_off cdr_pll_uc_ro_cal cdr_pll_uc_ro_cal uc_ro_cal_off cdr_pll_uc_ro_cal_status cdr_pll_uc_ro_cal_status uc_ro_sta_off cdr_pll_vco_bypass cdr_pll_vco_bypass false cdr_pll_vco_freq cdr_pll_vco_freq 10312500000 cdr_pll_vco_overrange_voltage cdr_pll_vco_overrange_voltage vco_overrange_off cdr_pll_vco_underrange_voltage cdr_pll_vco_underrange_voltage vco_underange_off cdr_pll_vreg_output cdr_pll_vreg_output vccdreg_nominal cdr_pll_direct_fb cdr_pll_direct_fb direct_fb cdr_pll_iqclk_sel cdr_pll_iqclk_sel power_down cdr_pll_silicon_rev cdr_pll_silicon_rev 14nm5bcr2eb cdr_pll_pma_width cdr_pll_pma_width 64 cdr_pll_cgb_div cdr_pll_cgb_div 1 cdr_pll_is_cascaded_pll cdr_pll_is_cascaded_pll false pma_rx_buf_act_isource_disable pma_rx_buf_act_isource_disable isrc_dis pma_rx_buf_advanced_mode pma_rx_buf_advanced_mode false pma_rx_buf_pm_cr2_rx_path_analog_mode pma_rx_buf_pm_cr2_rx_path_analog_mode user_custom pma_rx_buf_bodybias_enable pma_rx_buf_bodybias_enable bodybias_en pma_rx_buf_bodybias_select pma_rx_buf_bodybias_select bodybias_sel1 pma_rx_buf_pm_cr2_rx_path_bti_protected pma_rx_buf_pm_cr2_rx_path_bti_protected false pma_rx_buf_bypass_ctle_rf_cal pma_rx_buf_bypass_ctle_rf_cal use_dprio_rfcal pma_rx_buf_xrx_path_xcdr_deser_xcdr_cdr_d2a_enb pma_rx_buf_xrx_path_xcdr_deser_xcdr_cdr_d2a_enb bti_d2a_disable pma_rx_buf_clk_divrx_en pma_rx_buf_clk_divrx_en normal_clk pma_rx_buf_const_gm_en pma_rx_buf_const_gm_en cgm_en_3 pma_rx_buf_ctle_ac_gain pma_rx_buf_ctle_ac_gain 0 pma_rx_buf_ctle_eq_gain pma_rx_buf_ctle_eq_gain 0 pma_rx_buf_ctle_hires_bypass pma_rx_buf_ctle_hires_bypass ctle_hires_en pma_rx_buf_ctle_oc_coeff pma_rx_buf_ctle_oc_coeff 0 pma_rx_buf_ctle_oc_ib_sel pma_rx_buf_ctle_oc_ib_sel ib_oc_bw3 pma_rx_buf_ctle_oc_sign pma_rx_buf_ctle_oc_sign add_i_2_p_eq pma_rx_buf_ctle_rf_cal pma_rx_buf_ctle_rf_cal 3 pma_rx_buf_ctle_tia_isel pma_rx_buf_ctle_tia_isel ib_tia_bw1 pma_rx_buf_pm_cr2_tx_rx_cvp_mode pma_rx_buf_pm_cr2_tx_rx_cvp_mode cvp_off pma_rx_buf_datarate_bps pma_rx_buf_datarate_bps 10312500000 pma_rx_buf_pm_cr2_rx_path_datarate_bps pma_rx_buf_pm_cr2_rx_path_datarate_bps 10312500000 pma_rx_buf_pm_cr2_rx_path_datawidth pma_rx_buf_pm_cr2_rx_path_datawidth 64 pma_rx_buf_dfe_err_cal_en pma_rx_buf_dfe_err_cal_en dfe_err_cal_enb pma_rx_buf_dfe_err_sw_togg pma_rx_buf_dfe_err_sw_togg dfe_err_tog_a pma_rx_buf_dfe_h1_cal_en pma_rx_buf_dfe_h1_cal_en dfe_h1_cal_disable pma_rx_buf_dfe_h1_sw_togg pma_rx_buf_dfe_h1_sw_togg dfe_h1_tog_neg pma_rx_buf_diag_lp_en pma_rx_buf_diag_lp_en dlp_off pma_rx_buf_eq_bw_sel pma_rx_buf_eq_bw_sel eq_bw_1 pma_rx_buf_eq_cdgen_sel pma_rx_buf_eq_cdgen_sel eq_cdgen_2 pma_rx_buf_eq_isel pma_rx_buf_eq_isel eq_isel_1 pma_rx_buf_eq_sel pma_rx_buf_eq_sel eq_sel_1 pma_rx_buf_pm_cr2_rx_path_gt_enabled pma_rx_buf_pm_cr2_rx_path_gt_enabled disable pma_rx_buf_initial_settings pma_rx_buf_initial_settings true pma_rx_buf_pm_cr2_rx_path_initial_settings pma_rx_buf_pm_cr2_rx_path_initial_settings true pma_rx_buf_pm_cr2_rx_path_io_std pma_rx_buf_pm_cr2_rx_path_io_std io_off pma_rx_buf_pm_cr2_rx_path_jtag_hys pma_rx_buf_pm_cr2_rx_path_jtag_hys hys_increase_disable pma_rx_buf_pm_cr2_rx_path_jtag_lp pma_rx_buf_pm_cr2_rx_path_jtag_lp lp_off pma_rx_buf_link pma_rx_buf_link link_off pma_rx_buf_pm_cr2_rx_path_link pma_rx_buf_pm_cr2_rx_path_link sr pma_rx_buf_xrx_path_xcdr_deser_xcdr_loopback_mode pma_rx_buf_xrx_path_xcdr_deser_xcdr_loopback_mode loopback_disabled pma_rx_buf_loopback_modes pma_rx_buf_loopback_modes lpbk_disable pma_rx_buf_offset_cancellation_coarse pma_rx_buf_offset_cancellation_coarse coarse_setting_0 pma_rx_buf_offset_rx_cal_en pma_rx_buf_offset_rx_cal_en rx_oc_dis pma_rx_buf_optimal pma_rx_buf_optimal true pma_rx_buf_pm_cr2_rx_path_optimal pma_rx_buf_pm_cr2_rx_path_optimal true pma_rx_buf_pm_cr2_tx_rx_pcie_gen pma_rx_buf_pm_cr2_tx_rx_pcie_gen non_pcie pma_rx_buf_pm_cr2_tx_rx_pcie_gen_bitwidth pma_rx_buf_pm_cr2_tx_rx_pcie_gen_bitwidth pcie_gen3_32b pma_rx_buf_pdb_rx pma_rx_buf_pdb_rx normal_rx_on pma_rx_buf_pm_cr2_rx_path_pma_rx_divclk_hz pma_rx_buf_pm_cr2_rx_path_pma_rx_divclk_hz 161132812 pma_rx_buf_power_mode pma_rx_buf_power_mode mid_power pma_rx_buf_pm_cr2_rx_path_power_mode pma_rx_buf_pm_cr2_rx_path_power_mode mid_power pma_rx_buf_pm_cr2_rx_path_power_rail_eht pma_rx_buf_pm_cr2_rx_path_power_rail_eht 0 pma_rx_buf_power_rail_er pma_rx_buf_power_rail_er 0 pma_rx_buf_pm_cr2_rx_path_power_rail_er pma_rx_buf_pm_cr2_rx_path_power_rail_er 1030 pma_rx_buf_powermode_ac_aoc pma_rx_buf_powermode_ac_aoc aoc_pwr_ac_off pma_rx_buf_powermode_ac_ctle pma_rx_buf_powermode_ac_ctle ctle_pwr_ac2 pma_rx_buf_powermode_ac_vcm pma_rx_buf_powermode_ac_vcm vcm_pwr_ac3 pma_rx_buf_powermode_ac_vga pma_rx_buf_powermode_ac_vga vga_pwr_ac_half pma_rx_buf_powermode_dc_aoc pma_rx_buf_powermode_dc_aoc powerdown_aoc pma_rx_buf_powermode_dc_ctle pma_rx_buf_powermode_dc_ctle ctle_pwr_dc1 pma_rx_buf_powermode_dc_vcm pma_rx_buf_powermode_dc_vcm vcm_pwr_dc3 pma_rx_buf_powermode_dc_vga pma_rx_buf_powermode_dc_vga vga_pwr_dc_half pma_rx_buf_prot_mode pma_rx_buf_prot_mode basic_rx pma_rx_buf_pm_cr2_rx_path_prot_mode pma_rx_buf_pm_cr2_rx_path_prot_mode basic_rx pma_rx_buf_qpi_afe_en pma_rx_buf_qpi_afe_en ctle_mode_en pma_rx_buf_qpi_enable pma_rx_buf_qpi_enable non_qpi_mode pma_rx_buf_refclk_en pma_rx_buf_refclk_en disable pma_rx_buf_reserve_rx_channel pma_rx_buf_reserve_rx_channel false pma_rx_buf_rx_afe_oc_mode pma_rx_buf_rx_afe_oc_mode normal_op pma_rx_buf_rx_aoc_doc pma_rx_buf_rx_aoc_doc lower_dac_l0 pma_rx_buf_rx_atb_select pma_rx_buf_rx_atb_select atb_disable pma_rx_buf_rx_lfeq_enable pma_rx_buf_rx_lfeq_enable rx_lfeq_disable pma_rx_buf_rx_ltr_load_init pma_rx_buf_rx_ltr_load_init rx_load_original pma_rx_buf_rx_oc_or_lfeq_coeff pma_rx_buf_rx_oc_or_lfeq_coeff 0 pma_rx_buf_rx_pin_as_refclk_mode pma_rx_buf_rx_pin_as_refclk_mode false pma_rx_buf_rx_refclk_divider pma_rx_buf_rx_refclk_divider bypass_divider pma_rx_buf_rx_vga_oc_en pma_rx_buf_rx_vga_oc_en vga_cal_off pma_rx_buf_sel_vcm_ctle pma_rx_buf_sel_vcm_ctle vocm_eq_gndref pma_rx_buf_sel_vcm_tia pma_rx_buf_sel_vcm_tia vocm_tia_fixed pma_rx_buf_pm_cr2_rx_path_speed_grade pma_rx_buf_pm_cr2_rx_path_speed_grade e2 pma_rx_buf_sup_mode pma_rx_buf_sup_mode user_mode pma_rx_buf_pm_cr2_rx_path_sup_mode pma_rx_buf_pm_cr2_rx_path_sup_mode user_mode pma_rx_buf_term_sel pma_rx_buf_term_sel r_r4 pma_rx_buf_term_sync_bypass pma_rx_buf_term_sync_bypass bypass_termsync pma_rx_buf_term_tri_enable pma_rx_buf_term_tri_enable disable_tri pma_rx_buf_pm_cr2_tx_rx_testmux_select pma_rx_buf_pm_cr2_tx_rx_testmux_select setting0 pma_rx_buf_tia_sel pma_rx_buf_tia_sel tia_sel_1 pma_rx_buf_pm_cr2_rx_path_tile_type pma_rx_buf_pm_cr2_rx_path_tile_type h pma_rx_buf_pm_cr2_rx_path_uc_cal_clk_bypass pma_rx_buf_pm_cr2_rx_path_uc_cal_clk_bypass cal_clk_0 pma_rx_buf_pm_cr2_rx_path_uc_cal_enable pma_rx_buf_pm_cr2_rx_path_uc_cal_enable rx_cal_off pma_rx_buf_pm_cr2_rx_path_uc_cru_rstb pma_rx_buf_pm_cr2_rx_path_uc_cru_rstb cdr_lf_reset_off pma_rx_buf_pm_cr2_tx_rx_uc_odi_eye_left pma_rx_buf_pm_cr2_tx_rx_uc_odi_eye_left uc_odi_eye_left_off pma_rx_buf_pm_cr2_tx_rx_uc_odi_eye_right pma_rx_buf_pm_cr2_tx_rx_uc_odi_eye_right uc_odi_eye_right_off pma_rx_buf_pm_cr2_rx_path_uc_pcie_sw pma_rx_buf_pm_cr2_rx_path_uc_pcie_sw uc_pcie_gen1 pma_rx_buf_pm_cr2_tx_rx_uc_rx_cal pma_rx_buf_pm_cr2_tx_rx_uc_rx_cal uc_rx_cal_on pma_rx_buf_pm_cr2_rx_path_uc_rx_rstb pma_rx_buf_pm_cr2_rx_path_uc_rx_rstb rx_reset_on pma_rx_buf_vcm_cal_i pma_rx_buf_vcm_cal_i 4 pma_rx_buf_vcm_current_add pma_rx_buf_vcm_current_add vcm_current_3 pma_rx_buf_vcm_sel pma_rx_buf_vcm_sel vcm_l1 pma_rx_buf_vcm_sel_vccref pma_rx_buf_vcm_sel_vccref 5 pma_rx_buf_vga_dc_gain pma_rx_buf_vga_dc_gain 0 pma_rx_buf_vga_halfbw_en pma_rx_buf_vga_halfbw_en vga_half_bw_enabled pma_rx_buf_vga_ib_max_en pma_rx_buf_vga_ib_max_en vga_ib_max_disable pma_rx_buf_vga_mode pma_rx_buf_vga_mode vga_off pma_rx_buf_silicon_rev pma_rx_buf_silicon_rev 14nm5bcr2eb pma_rx_deser_bitslip_bypass pma_rx_deser_bitslip_bypass bs_bypass_yes pma_rx_deser_bti_protected pma_rx_deser_bti_protected false pma_rx_deser_clkdiv_source pma_rx_deser_clkdiv_source vco_bypass_normal pma_rx_deser_clkdivrx_user_mode pma_rx_deser_clkdivrx_user_mode clkdivrx_user_div33 pma_rx_deser_datarate_bps pma_rx_deser_datarate_bps 10312500000 pma_rx_deser_deser_aib_dftppm_en pma_rx_deser_deser_aib_dftppm_en disable pma_rx_deser_deser_aibck_en pma_rx_deser_deser_aibck_en enable pma_rx_deser_deser_aibck_x1 pma_rx_deser_deser_aibck_x1 normal pma_rx_deser_deser_factor pma_rx_deser_deser_factor deser_64b pma_rx_deser_deser_powerdown pma_rx_deser_deser_powerdown deser_power_up pma_rx_deser_force_adaptation_outputs pma_rx_deser_force_adaptation_outputs normal_outputs pma_rx_deser_force_clkdiv_for_testing pma_rx_deser_force_clkdiv_for_testing normal_clkdiv pma_rx_deser_odi_adapt_bti_en pma_rx_deser_odi_adapt_bti_en deser_bti_disable pma_rx_deser_optimal pma_rx_deser_optimal true pma_rx_deser_pcie_g3_hclk_en pma_rx_deser_pcie_g3_hclk_en disable_hclk_div2 pma_rx_deser_pm_cr2_tx_rx_pcie_gen pma_rx_deser_pm_cr2_tx_rx_pcie_gen non_pcie pma_rx_deser_pm_cr2_tx_rx_pcie_gen_bitwidth pma_rx_deser_pm_cr2_tx_rx_pcie_gen_bitwidth pcie_gen3_32b pma_rx_deser_powermode_ac_deser pma_rx_deser_powermode_ac_deser deser_ac_64b_nobs pma_rx_deser_powermode_ac_deser_bs pma_rx_deser_powermode_ac_deser_bs deser_ac_bs_off pma_rx_deser_powermode_dc_deser pma_rx_deser_powermode_dc_deser deser_dc_64b_nobs pma_rx_deser_powermode_dc_deser_bs pma_rx_deser_powermode_dc_deser_bs powerdown_deser_bs pma_rx_deser_prot_mode pma_rx_deser_prot_mode basic_rx pma_rx_deser_rst_n_adapt_odi pma_rx_deser_rst_n_adapt_odi no_rst_adapt_odi pma_rx_deser_sd_clk pma_rx_deser_sd_clk sd_clk_disabled pma_rx_deser_sup_mode pma_rx_deser_sup_mode user_mode pma_rx_deser_tdr_mode pma_rx_deser_tdr_mode select_bbpd_data pma_rx_deser_silicon_rev pma_rx_deser_silicon_rev 14nm5bcr2eb pma_rx_dfe_adapt_bti_en pma_rx_dfe_adapt_bti_en adapt_bti_disable pma_rx_dfe_atb_select pma_rx_dfe_atb_select atb_disable pma_rx_dfe_bti_protected pma_rx_dfe_bti_protected false pma_rx_dfe_xrx_path_xcdr_deser_xcdr_cdr_d2a_enb pma_rx_dfe_xrx_path_xcdr_deser_xcdr_cdr_d2a_enb bti_d2a_disable pma_rx_dfe_datarate_bps pma_rx_dfe_datarate_bps 10312500000 pma_rx_dfe_dfe_bti_en pma_rx_dfe_dfe_bti_en dfe_bti_disable pma_rx_dfe_dfe_mode pma_rx_dfe_dfe_mode cdr_mode pma_rx_dfe_dft_en pma_rx_dfe_dft_en dft_disable pma_rx_dfe_dft_hilospeed_sel pma_rx_dfe_dft_hilospeed_sel dft_osc_lospeed_path pma_rx_dfe_dft_osc_sel pma_rx_dfe_dft_osc_sel dft_osc_even pma_rx_dfe_h1edge_bti_en pma_rx_dfe_h1edge_bti_en h1edge_bti_disable pma_rx_dfe_initial_settings pma_rx_dfe_initial_settings true pma_rx_dfe_latch_xcouple_disable pma_rx_dfe_latch_xcouple_disable latch_xcouple_enable pma_rx_dfe_oc_sa_cdr0e pma_rx_dfe_oc_sa_cdr0e 0 pma_rx_dfe_oc_sa_cdr0e_sgn pma_rx_dfe_oc_sa_cdr0e_sgn oc_sa_cdr0e_sgn_0 pma_rx_dfe_oc_sa_cdr0o pma_rx_dfe_oc_sa_cdr0o 0 pma_rx_dfe_oc_sa_cdr0o_sgn pma_rx_dfe_oc_sa_cdr0o_sgn oc_sa_cdr0o_sgn_0 pma_rx_dfe_oc_sa_cdrne pma_rx_dfe_oc_sa_cdrne 0 pma_rx_dfe_oc_sa_cdrne_sgn pma_rx_dfe_oc_sa_cdrne_sgn oc_sa_cdrne_sgn_0 pma_rx_dfe_oc_sa_cdrno pma_rx_dfe_oc_sa_cdrno 0 pma_rx_dfe_oc_sa_cdrno_sgn pma_rx_dfe_oc_sa_cdrno_sgn oc_sa_cdrno_sgn_0 pma_rx_dfe_oc_sa_cdrpe pma_rx_dfe_oc_sa_cdrpe 0 pma_rx_dfe_oc_sa_cdrpe_sgn pma_rx_dfe_oc_sa_cdrpe_sgn oc_sa_cdrpe_sgn_0 pma_rx_dfe_oc_sa_cdrpo pma_rx_dfe_oc_sa_cdrpo 0 pma_rx_dfe_oc_sa_cdrpo_sgn pma_rx_dfe_oc_sa_cdrpo_sgn oc_sa_cdrpo_sgn_0 pma_rx_dfe_oc_sa_dne pma_rx_dfe_oc_sa_dne 0 pma_rx_dfe_oc_sa_dne_sgn pma_rx_dfe_oc_sa_dne_sgn oc_sa_dne_sgn_0 pma_rx_dfe_oc_sa_dno pma_rx_dfe_oc_sa_dno 0 pma_rx_dfe_oc_sa_dno_sgn pma_rx_dfe_oc_sa_dno_sgn oc_sa_dno_sgn_0 pma_rx_dfe_oc_sa_dpe pma_rx_dfe_oc_sa_dpe 0 pma_rx_dfe_oc_sa_dpe_sgn pma_rx_dfe_oc_sa_dpe_sgn oc_sa_dpe_sgn_0 pma_rx_dfe_oc_sa_dpo pma_rx_dfe_oc_sa_dpo 0 pma_rx_dfe_oc_sa_dpo_sgn pma_rx_dfe_oc_sa_dpo_sgn oc_sa_dpo_sgn_0 pma_rx_dfe_oc_sa_odie pma_rx_dfe_oc_sa_odie 0 pma_rx_dfe_oc_sa_odie_sgn pma_rx_dfe_oc_sa_odie_sgn oc_sa_odie_sgn_0 pma_rx_dfe_oc_sa_odio pma_rx_dfe_oc_sa_odio 0 pma_rx_dfe_oc_sa_odio_sgn pma_rx_dfe_oc_sa_odio_sgn oc_sa_odio_sgn_0 pma_rx_dfe_oc_sa_vrefe pma_rx_dfe_oc_sa_vrefe 0 pma_rx_dfe_oc_sa_vrefe_sgn pma_rx_dfe_oc_sa_vrefe_sgn oc_sa_vrefe_sgn_0 pma_rx_dfe_oc_sa_vrefo pma_rx_dfe_oc_sa_vrefo 0 pma_rx_dfe_oc_sa_vrefo_sgn pma_rx_dfe_oc_sa_vrefo_sgn oc_sa_vrefo_sgn_0 pma_rx_dfe_odi_bti_en pma_rx_dfe_odi_bti_en odi_bti_disable pma_rx_dfe_odi_dlev_sign pma_rx_dfe_odi_dlev_sign odi_dlev_pos pma_rx_dfe_odi_h1_sign pma_rx_dfe_odi_h1_sign odi_h1_pos pma_rx_dfe_optimal pma_rx_dfe_optimal true pma_rx_dfe_pdb pma_rx_dfe_pdb dfe_enable pma_rx_dfe_pdb_edge_pre_h1 pma_rx_dfe_pdb_edge_pre_h1 cdr_pre_h1_enable pma_rx_dfe_pdb_edge_pst_h1 pma_rx_dfe_pdb_edge_pst_h1 cdr_pst_h1_disable pma_rx_dfe_pdb_tap_10t15 pma_rx_dfe_pdb_tap_10t15 tap10t15_dfe_powerdown pma_rx_dfe_pdb_tap_4t9 pma_rx_dfe_pdb_tap_4t9 tap4t9_dfe_powerdown pma_rx_dfe_pdb_tapsum pma_rx_dfe_pdb_tapsum tapsum_disable pma_rx_dfe_power_mode pma_rx_dfe_power_mode mid_power pma_rx_dfe_powermode_ac_dfe pma_rx_dfe_powermode_ac_dfe ac_cdr_mode pma_rx_dfe_powermode_dc_dfe pma_rx_dfe_powermode_dc_dfe powerdown_dfe pma_rx_dfe_prot_mode pma_rx_dfe_prot_mode basic_rx pma_rx_dfe_sel_oc_en pma_rx_dfe_sel_oc_en off_canc_disable pma_rx_dfe_sel_probe_tstmx pma_rx_dfe_sel_probe_tstmx probe_tstmx_none pma_rx_dfe_sup_mode pma_rx_dfe_sup_mode user_mode pma_rx_dfe_tap10_coeff pma_rx_dfe_tap10_coeff 0 pma_rx_dfe_tap10_sgn pma_rx_dfe_tap10_sgn tap10_sign_0 pma_rx_dfe_tap11_coeff pma_rx_dfe_tap11_coeff 0 pma_rx_dfe_tap11_sgn pma_rx_dfe_tap11_sgn tap11_sign_0 pma_rx_dfe_tap12_coeff pma_rx_dfe_tap12_coeff 0 pma_rx_dfe_tap12_sgn pma_rx_dfe_tap12_sgn tap12_sign_0 pma_rx_dfe_tap13_coeff pma_rx_dfe_tap13_coeff 0 pma_rx_dfe_tap13_sgn pma_rx_dfe_tap13_sgn tap13_sign_0 pma_rx_dfe_tap14_coeff pma_rx_dfe_tap14_coeff 0 pma_rx_dfe_tap14_sgn pma_rx_dfe_tap14_sgn tap14_sign_0 pma_rx_dfe_tap15_coeff pma_rx_dfe_tap15_coeff 0 pma_rx_dfe_tap15_sgn pma_rx_dfe_tap15_sgn tap15_sign_0 pma_rx_dfe_tap1_coeff pma_rx_dfe_tap1_coeff 0 pma_rx_dfe_tap1_sgn pma_rx_dfe_tap1_sgn tap1_sign_0 pma_rx_dfe_tap2_coeff pma_rx_dfe_tap2_coeff 0 pma_rx_dfe_tap2_sgn pma_rx_dfe_tap2_sgn tap2_sign_0 pma_rx_dfe_tap3_coeff pma_rx_dfe_tap3_coeff 0 pma_rx_dfe_tap3_sgn pma_rx_dfe_tap3_sgn tap3_sign_0 pma_rx_dfe_tap4_coeff pma_rx_dfe_tap4_coeff 0 pma_rx_dfe_tap4_sgn pma_rx_dfe_tap4_sgn tap4_sign_0 pma_rx_dfe_tap5_coeff pma_rx_dfe_tap5_coeff 0 pma_rx_dfe_tap5_sgn pma_rx_dfe_tap5_sgn tap5_sign_0 pma_rx_dfe_tap6_coeff pma_rx_dfe_tap6_coeff 0 pma_rx_dfe_tap6_sgn pma_rx_dfe_tap6_sgn tap6_sign_0 pma_rx_dfe_tap7_coeff pma_rx_dfe_tap7_coeff 0 pma_rx_dfe_tap7_sgn pma_rx_dfe_tap7_sgn tap7_sign_0 pma_rx_dfe_tap8_coeff pma_rx_dfe_tap8_coeff 0 pma_rx_dfe_tap8_sgn pma_rx_dfe_tap8_sgn tap8_sign_0 pma_rx_dfe_tap9_coeff pma_rx_dfe_tap9_coeff 0 pma_rx_dfe_tap9_sgn pma_rx_dfe_tap9_sgn tap9_sign_0 pma_rx_dfe_tapsum_bw_sel pma_rx_dfe_tapsum_bw_sel tapsum_medbw pma_rx_dfe_vref_coeff pma_rx_dfe_vref_coeff 0 pma_rx_dfe_silicon_rev pma_rx_dfe_silicon_rev 14nm5bcr2eb pma_rx_odi_datarate_bps pma_rx_odi_datarate_bps 10312500000 pma_rx_odi_enable_cdr_lpbk pma_rx_odi_enable_cdr_lpbk disable_lpbk pma_rx_odi_initial_settings pma_rx_odi_initial_settings true pma_rx_odi_monitor_bw_sel pma_rx_odi_monitor_bw_sel bw_4 pma_rx_odi_optimal pma_rx_odi_optimal true pma_rx_odi_phase_steps_64_vs_128 pma_rx_odi_phase_steps_64_vs_128 phase_steps_64 pma_rx_odi_phase_steps_sel pma_rx_odi_phase_steps_sel step33 pma_rx_odi_power_mode pma_rx_odi_power_mode mid_power pma_rx_odi_prot_mode pma_rx_odi_prot_mode basic_rx pma_rx_odi_xrx_path_x119_rx_path_rstn_overrideb pma_rx_odi_xrx_path_x119_rx_path_rstn_overrideb use_sequencer pma_rx_odi_step_ctrl_sel pma_rx_odi_step_ctrl_sel dprio_mode pma_rx_odi_sup_mode pma_rx_odi_sup_mode user_mode pma_rx_odi_vert_threshold pma_rx_odi_vert_threshold vert_0 pma_rx_odi_vreg_voltage_sel pma_rx_odi_vreg_voltage_sel vreg0 pma_rx_odi_silicon_rev pma_rx_odi_silicon_rev 14nm5bcr2eb pma_rx_sd_link pma_rx_sd_link sr pma_rx_sd_optimal pma_rx_sd_optimal true pma_rx_sd_power_mode pma_rx_sd_power_mode mid_power pma_rx_sd_powermode_ac_sd pma_rx_sd_powermode_ac_sd ac_off_sd pma_rx_sd_powermode_dc_sd pma_rx_sd_powermode_dc_sd powerdown_sd pma_rx_sd_prot_mode pma_rx_sd_prot_mode basic_rx pma_rx_sd_sd_output_off pma_rx_sd_sd_output_off clk_divrx_2 pma_rx_sd_sd_output_on pma_rx_sd_sd_output_on force_sd_output_on pma_rx_sd_sd_pdb pma_rx_sd_sd_pdb sd_off pma_rx_sd_sd_threshold pma_rx_sd_sd_threshold sdlv_3 pma_rx_sd_sup_mode pma_rx_sd_sup_mode user_mode pma_rx_sd_silicon_rev pma_rx_sd_silicon_rev 14nm5bcr2eb pma_tx_buf_pm_cr2_tx_path_analog_mode pma_tx_buf_pm_cr2_tx_path_analog_mode user_custom pma_tx_buf_pm_cr2_tx_path_bonding_mode pma_tx_buf_pm_cr2_tx_path_bonding_mode x1_non_bonded pma_tx_buf_bti_protected pma_tx_buf_bti_protected false pma_tx_buf_calibration_en pma_tx_buf_calibration_en false pma_tx_buf_pm_cr2_tx_path_calibration_en pma_tx_buf_pm_cr2_tx_path_calibration_en false pma_tx_buf_calibration_resistor_value pma_tx_buf_calibration_resistor_value res_setting0 pma_tx_buf_cdr_cp_calibration_en pma_tx_buf_cdr_cp_calibration_en cdr_cp_cal_disable pma_tx_buf_chgpmp_current_dn_trim pma_tx_buf_chgpmp_current_dn_trim cp_current_trimming_dn_setting0 pma_tx_buf_chgpmp_current_up_trim pma_tx_buf_chgpmp_current_up_trim cp_current_trimming_up_setting0 pma_tx_buf_chgpmp_dn_trim_double pma_tx_buf_chgpmp_dn_trim_double normal_dn_trim_current pma_tx_buf_chgpmp_up_trim_double pma_tx_buf_chgpmp_up_trim_double normal_up_trim_current pma_tx_buf_pm_cr2_tx_path_clock_divider_ratio pma_tx_buf_pm_cr2_tx_path_clock_divider_ratio 1 pma_tx_buf_compensation_en pma_tx_buf_compensation_en enable pma_tx_buf_compensation_posttap_en pma_tx_buf_compensation_posttap_en disable pma_tx_buf_cpen_ctrl pma_tx_buf_cpen_ctrl cp_l1 pma_tx_buf_data_dcc_setting pma_tx_buf_data_dcc_setting ddcc_disable pma_tx_buf_datarate_bps pma_tx_buf_datarate_bps 10312500000 pma_tx_buf_pm_cr2_tx_path_datarate_bps pma_tx_buf_pm_cr2_tx_path_datarate_bps 10312500000 pma_tx_buf_pm_cr2_tx_path_datawidth pma_tx_buf_pm_cr2_tx_path_datawidth 64 pma_tx_buf_dcc_finestep_enin pma_tx_buf_dcc_finestep_enin disable pma_tx_buf_dcd_clk_div_ctrl pma_tx_buf_dcd_clk_div_ctrl dcd_ck_div128 pma_tx_buf_dcd_detection_en pma_tx_buf_dcd_detection_en disable pma_tx_buf_dft_sel pma_tx_buf_dft_sel dft_disabled pma_tx_buf_duty_cycle_correction_bandwidth pma_tx_buf_duty_cycle_correction_bandwidth dcc_bw_2 pma_tx_buf_duty_cycle_correction_bandwidth_dn pma_tx_buf_duty_cycle_correction_bandwidth_dn dcd_bw_dn_2 pma_tx_buf_duty_cycle_correction_reference1 pma_tx_buf_duty_cycle_correction_reference1 dcc_ref1_4 pma_tx_buf_duty_cycle_correction_reference2 pma_tx_buf_duty_cycle_correction_reference2 dcc_ref2_2 pma_tx_buf_duty_cycle_correction_reset_n pma_tx_buf_duty_cycle_correction_reset_n reset pma_tx_buf_duty_cycle_cp_comp_en pma_tx_buf_duty_cycle_cp_comp_en cp_comp_off pma_tx_buf_duty_cycle_detector_cp_cal pma_tx_buf_duty_cycle_detector_cp_cal dcd_cp_cal_disable pma_tx_buf_duty_cycle_detector_sa_cal pma_tx_buf_duty_cycle_detector_sa_cal dcd_sa_cal_disable pma_tx_buf_duty_cycle_input_polarity pma_tx_buf_duty_cycle_input_polarity dcc_input_pos pma_tx_buf_duty_cycle_setting pma_tx_buf_duty_cycle_setting dcc_t32 pma_tx_buf_duty_cycle_setting_aux pma_tx_buf_duty_cycle_setting_aux dcc2_t32 pma_tx_buf_enable_idle_tx_channel_support pma_tx_buf_enable_idle_tx_channel_support false pma_tx_buf_pm_cr2_tx_path_gt_enabled pma_tx_buf_pm_cr2_tx_path_gt_enabled disable pma_tx_buf_idle_ctrl pma_tx_buf_idle_ctrl id_cpen_on pma_tx_buf_initial_settings pma_tx_buf_initial_settings true pma_tx_buf_pm_cr2_tx_path_initial_settings pma_tx_buf_pm_cr2_tx_path_initial_settings true pma_tx_buf_jtag_drv_sel pma_tx_buf_jtag_drv_sel drv1 pma_tx_buf_jtag_lp pma_tx_buf_jtag_lp lp_off pma_tx_buf_link pma_tx_buf_link link_off pma_tx_buf_pm_cr2_tx_path_link pma_tx_buf_pm_cr2_tx_path_link sr pma_tx_buf_low_power_en pma_tx_buf_low_power_en disable pma_tx_buf_lst pma_tx_buf_lst atb_disabled pma_tx_buf_pm_cr2_tx_rx_mcgb_location_for_pcie pma_tx_buf_pm_cr2_tx_rx_mcgb_location_for_pcie 0 pma_tx_buf_optimal pma_tx_buf_optimal true pma_tx_buf_pm_cr2_tx_path_optimal pma_tx_buf_pm_cr2_tx_path_optimal true pma_tx_buf_pcie_gen pma_tx_buf_pcie_gen non_pcie pma_tx_buf_pm_cr2_tx_path_pma_tx_divclk_hz pma_tx_buf_pm_cr2_tx_path_pma_tx_divclk_hz 161132812 pma_tx_buf_pm_cr2_tx_path_power_mode pma_tx_buf_pm_cr2_tx_path_power_mode mid_power pma_tx_buf_pm_cr2_tx_path_power_rail_eht pma_tx_buf_pm_cr2_tx_path_power_rail_eht 1800 pma_tx_buf_power_rail_er pma_tx_buf_power_rail_er 0 pma_tx_buf_pm_cr2_tx_path_power_rail_et pma_tx_buf_pm_cr2_tx_path_power_rail_et 1030 pma_tx_buf_powermode_ac_post_tap pma_tx_buf_powermode_ac_post_tap tx_post_tap_ac_off pma_tx_buf_powermode_ac_pre_tap pma_tx_buf_powermode_ac_pre_tap tx_pre_tap_ac_off pma_tx_buf_powermode_ac_tx_vod_no_jitcomp pma_tx_buf_powermode_ac_tx_vod_no_jitcomp tx_vod_no_jitcomp_ac_l0 pma_tx_buf_powermode_ac_tx_vod_w_jitcomp pma_tx_buf_powermode_ac_tx_vod_w_jitcomp tx_vod_w_jitcomp_ac_l31 pma_tx_buf_powermode_dc_post_tap pma_tx_buf_powermode_dc_post_tap powerdown_tx_post_tap pma_tx_buf_powermode_dc_pre_tap pma_tx_buf_powermode_dc_pre_tap powerdown_tx_pre_tap pma_tx_buf_powermode_dc_tx_vod_no_jitcomp pma_tx_buf_powermode_dc_tx_vod_no_jitcomp powerdown_tx_vod_no_jitcomp pma_tx_buf_powermode_dc_tx_vod_w_jitcomp pma_tx_buf_powermode_dc_tx_vod_w_jitcomp tx_vod_w_jitcomp_dc_l31 pma_tx_buf_pre_emp_sign_1st_post_tap pma_tx_buf_pre_emp_sign_1st_post_tap fir_post_1t_neg pma_tx_buf_pre_emp_sign_pre_tap_1t pma_tx_buf_pre_emp_sign_pre_tap_1t fir_pre_1t_neg pma_tx_buf_pre_emp_switching_ctrl_1st_post_tap pma_tx_buf_pre_emp_switching_ctrl_1st_post_tap 0 pma_tx_buf_pre_emp_switching_ctrl_pre_tap_1t pma_tx_buf_pre_emp_switching_ctrl_pre_tap_1t 0 pma_tx_buf_prot_mode pma_tx_buf_prot_mode basic_tx pma_tx_buf_pm_cr2_tx_path_prot_mode pma_tx_buf_pm_cr2_tx_path_prot_mode basic_tx pma_tx_buf_res_cal_local pma_tx_buf_res_cal_local non_local pma_tx_buf_reserve_tx_channel pma_tx_buf_reserve_tx_channel false pma_tx_buf_rx_det pma_tx_buf_rx_det mode_0 pma_tx_buf_rx_det_output_sel pma_tx_buf_rx_det_output_sel rx_det_pcie_out pma_tx_buf_rx_det_pdb pma_tx_buf_rx_det_pdb rx_det_off pma_tx_buf_sense_amp_offset_cal_curr_n pma_tx_buf_sense_amp_offset_cal_curr_n sa_os_cal_in_0 pma_tx_buf_sense_amp_offset_cal_curr_p pma_tx_buf_sense_amp_offset_cal_curr_p 0 pma_tx_buf_ser_powerdown pma_tx_buf_ser_powerdown normal_ser_on pma_tx_buf_slew_rate_ctrl pma_tx_buf_slew_rate_ctrl slew_r5 pma_tx_buf_pm_cr2_tx_path_speed_grade pma_tx_buf_pm_cr2_tx_path_speed_grade e2 pma_tx_buf_sup_mode pma_tx_buf_sup_mode user_mode pma_tx_buf_pm_cr2_tx_path_sup_mode pma_tx_buf_pm_cr2_tx_path_sup_mode user_mode pma_tx_buf_swing_level pma_tx_buf_swing_level hv pma_tx_buf_pm_cr2_tx_path_swing_level pma_tx_buf_pm_cr2_tx_path_swing_level hv pma_tx_buf_term_code pma_tx_buf_term_code rterm_code0 pma_tx_buf_term_n_tune pma_tx_buf_term_n_tune rterm_n7 pma_tx_buf_term_p_tune pma_tx_buf_term_p_tune rterm_p7 pma_tx_buf_term_sel pma_tx_buf_term_sel r_r1 pma_tx_buf_pm_cr2_tx_path_tile_type pma_tx_buf_pm_cr2_tx_path_tile_type h pma_tx_buf_tri_driver pma_tx_buf_tri_driver tri_driver_disable pma_tx_buf_pm_cr2_tx_path_tx_pll_clk_hz pma_tx_buf_pm_cr2_tx_path_tx_pll_clk_hz 5156250000 pma_tx_buf_tx_powerdown pma_tx_buf_tx_powerdown normal_tx_on pma_tx_buf_tx_rst_enable pma_tx_buf_tx_rst_enable enable pma_tx_buf_xtx_path_xcgb_tx_ucontrol_en pma_tx_buf_xtx_path_xcgb_tx_ucontrol_en disable pma_tx_buf_uc_gen3 pma_tx_buf_uc_gen3 gen3_off pma_tx_buf_uc_gen4 pma_tx_buf_uc_gen4 gen4_off pma_tx_buf_uc_tx_cal pma_tx_buf_uc_tx_cal uc_tx_cal_on pma_tx_buf_uc_vcc_setting pma_tx_buf_uc_vcc_setting vcc_setting1 pma_tx_buf_user_fir_coeff_ctrl_sel pma_tx_buf_user_fir_coeff_ctrl_sel ram_ctl pma_tx_buf_vod_output_swing_ctrl pma_tx_buf_vod_output_swing_ctrl 31 pma_tx_buf_vreg_output pma_tx_buf_vreg_output vccdreg_nominal pma_tx_buf_silicon_rev pma_tx_buf_silicon_rev 14nm5bcr2eb pma_cgb_bitslip_enable pma_cgb_bitslip_enable disable_bitslip pma_cgb_bonding_mode pma_cgb_bonding_mode bond_off pma_cgb_bti_protected pma_cgb_bti_protected false pma_cgb_cgb_bti_en pma_cgb_cgb_bti_en cgb_bti_disable pma_cgb_cgb_power_down pma_cgb_cgb_power_down normal_cgb pma_cgb_datarate_bps pma_cgb_datarate_bps 10312500000 pma_cgb_initial_settings pma_cgb_initial_settings true pma_cgb_observe_cgb_clocks pma_cgb_observe_cgb_clocks observe_nothing pma_cgb_pcie_gen pma_cgb_pcie_gen non_pcie pma_cgb_pcie_gen3_bitwidth pma_cgb_pcie_gen3_bitwidth pciegen3_wide pma_cgb_power_rail_er pma_cgb_power_rail_er 1030 pma_cgb_powermode_ac_cgb pma_cgb_powermode_ac_cgb cgb_ac_off pma_cgb_powermode_dc_cgb pma_cgb_powermode_dc_cgb powerdown_cgb pma_cgb_prot_mode pma_cgb_prot_mode basic_tx pma_cgb_scratch0_x1_clock_src pma_cgb_scratch0_x1_clock_src not_used pma_cgb_scratch1_x1_clock_src pma_cgb_scratch1_x1_clock_src not_used pma_cgb_scratch2_x1_clock_src pma_cgb_scratch2_x1_clock_src not_used pma_cgb_scratch3_x1_clock_src pma_cgb_scratch3_x1_clock_src not_used pma_cgb_select_done_master_or_slave pma_cgb_select_done_master_or_slave choose_slave_pcie_sw_done pma_cgb_ser_mode pma_cgb_ser_mode sixty_four_bit pma_cgb_ser_powerdown pma_cgb_ser_powerdown normal_poweron_ser pma_cgb_sup_mode pma_cgb_sup_mode user_mode pma_cgb_tx_ucontrol_en pma_cgb_tx_ucontrol_en disable pma_cgb_tx_ucontrol_pcie pma_cgb_tx_ucontrol_pcie gen1 pma_cgb_tx_ucontrol_reset pma_cgb_tx_ucontrol_reset disable pma_cgb_uc_cgb_vreg_boost pma_cgb_uc_cgb_vreg_boost no_voltage_boost pma_cgb_uc_vcc_setting pma_cgb_uc_vcc_setting vcc_setting1 pma_cgb_vccdreg_output pma_cgb_vccdreg_output vccdreg_nominal pma_cgb_vreg_sel_ref pma_cgb_vreg_sel_ref sel_vccer_4ref pma_cgb_x1_clock_source_sel pma_cgb_x1_clock_source_sel lcpll_top pma_cgb_x1_div_m_sel pma_cgb_x1_div_m_sel divbypass pma_cgb_xn_clock_source_sel pma_cgb_xn_clock_source_sel sel_cgb_loc pma_cgb_silicon_rev pma_cgb_silicon_rev 14nm5bcr2eb pma_cgb_input_select_x1 pma_cgb_input_select_x1 fpll_bot pma_cgb_input_select_gen3 pma_cgb_input_select_gen3 not_used pma_cgb_input_select_xn pma_cgb_input_select_xn not_used pma_tx_ser_bonding_mode pma_tx_ser_bonding_mode bond_off pma_tx_ser_bti_protected pma_tx_ser_bti_protected false pma_tx_ser_clk_divtx_deskew pma_tx_ser_clk_divtx_deskew deskew_delay0 pma_tx_ser_control_clks_divtx_aibtx pma_tx_ser_control_clks_divtx_aibtx no_dft_control_clkdivtx_clkaibtx pma_tx_ser_datarate_bps pma_tx_ser_datarate_bps 0 pma_tx_ser_duty_cycle_correction_mode_ctrl pma_tx_ser_duty_cycle_correction_mode_ctrl dcc_disable pma_tx_ser_xtx_path_xtx_idle_ctrl pma_tx_ser_xtx_path_xtx_idle_ctrl id_cpen_on pma_tx_ser_initial_settings pma_tx_ser_initial_settings true pma_tx_ser_pcie_gen pma_tx_ser_pcie_gen non_pcie pma_tx_ser_power_rail_er pma_tx_ser_power_rail_er 1030 pma_tx_ser_powermode_ac_ser pma_tx_ser_powermode_ac_ser ac_clk_divtx_user_33_jitcomp1p0 pma_tx_ser_powermode_dc_ser pma_tx_ser_powermode_dc_ser dc_clk_divtx_user_33_jitcomp1p0 pma_tx_ser_prot_mode pma_tx_ser_prot_mode basic_tx pma_tx_ser_ser_clk_divtx_user_sel pma_tx_ser_ser_clk_divtx_user_sel divtx_user_33 pma_tx_ser_ser_aibck_enable pma_tx_ser_ser_aibck_enable enable pma_tx_ser_ser_aibck_x1_override pma_tx_ser_ser_aibck_x1_override normal pma_tx_ser_ser_clk_mon pma_tx_ser_ser_clk_mon disable_clk_mon pma_tx_ser_ser_dftppm_clkselect pma_tx_ser_ser_dftppm_clkselect aib_dftppm pma_tx_ser_ser_in_jitcomp pma_tx_ser_ser_in_jitcomp jitcomp_on pma_tx_ser_ser_powerdown pma_tx_ser_ser_powerdown normal_poweron_ser pma_tx_ser_ser_preset_bti_en pma_tx_ser_ser_preset_bti_en ser_preset_bti_disable pma_tx_ser_sup_mode pma_tx_ser_sup_mode user_mode pma_tx_ser_uc_vcc_setting pma_tx_ser_uc_vcc_setting vcc_setting1 pma_tx_ser_silicon_rev pma_tx_ser_silicon_rev 14nm5bcr2eb pma_tx_ser_xtx_path_xchnseq_txpath_chnseq_idle_direct_on pma_tx_ser_xtx_path_xchnseq_txpath_chnseq_idle_direct_on cgb_idle_direct_off pma_reset_sequencer_rx_path_rstn_overrideb pma_reset_sequencer_rx_path_rstn_overrideb use_sequencer pma_reset_sequencer_xrx_path_uc_cal_clk_bypass pma_reset_sequencer_xrx_path_uc_cal_clk_bypass cal_clk_0 pma_reset_sequencer_xrx_path_uc_cal_enable pma_reset_sequencer_xrx_path_uc_cal_enable rx_cal_off pma_reset_sequencer_silicon_rev pma_reset_sequencer_silicon_rev 14nm5bcr2eb pma_tx_sequencer_tx_path_rstn_overrideb pma_tx_sequencer_tx_path_rstn_overrideb use_sequencer pma_tx_sequencer_xtx_path_xcgb_tx_ucontrol_en pma_tx_sequencer_xtx_path_xcgb_tx_ucontrol_en disable pma_tx_sequencer_xrx_path_uc_cal_clk_bypass pma_tx_sequencer_xrx_path_uc_cal_clk_bypass cal_clk_0 pma_tx_sequencer_silicon_rev pma_tx_sequencer_silicon_rev 14nm5bcr2eb pma_txpath_chnsequencer_pcie_gen pma_txpath_chnsequencer_pcie_gen non_pcie pma_txpath_chnsequencer_prot_mode pma_txpath_chnsequencer_prot_mode basic_tx pma_txpath_chnsequencer_sup_mode pma_txpath_chnsequencer_sup_mode sup_off pma_txpath_chnsequencer_txpath_chnseq_enable pma_txpath_chnsequencer_txpath_chnseq_enable disable pma_txpath_chnsequencer_txpath_chnseq_idle_direct_on pma_txpath_chnsequencer_txpath_chnseq_idle_direct_on cgb_idle_direct_off pma_txpath_chnsequencer_txpath_chnseq_stage_select pma_txpath_chnsequencer_txpath_chnseq_stage_select 0 pma_txpath_chnsequencer_txpath_chnseq_wakeup_bypass pma_txpath_chnsequencer_txpath_chnseq_wakeup_bypass bypass_off pma_txpath_chnsequencer_silicon_rev pma_txpath_chnsequencer_silicon_rev 14nm5bcr2ea hssi_fifo_rx_pcs_double_read_mode hssi_fifo_rx_pcs_double_read_mode double_read_dis hssi_fifo_rx_pcs_prot_mode hssi_fifo_rx_pcs_prot_mode teng_mode hssi_fifo_rx_pcs_silicon_rev hssi_fifo_rx_pcs_silicon_rev 14nm5bcr2eb hssi_fifo_tx_pcs_double_write_mode hssi_fifo_tx_pcs_double_write_mode double_write_dis hssi_fifo_tx_pcs_prot_mode hssi_fifo_tx_pcs_prot_mode teng_mode hssi_fifo_tx_pcs_silicon_rev hssi_fifo_tx_pcs_silicon_rev 14nm5bcr2eb hssi_gen3_rx_pcs_block_sync hssi_gen3_rx_pcs_block_sync bypass_block_sync hssi_gen3_rx_pcs_block_sync_sm hssi_gen3_rx_pcs_block_sync_sm disable_blk_sync_sm hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn disable hssi_gen3_rx_pcs_lpbk_force hssi_gen3_rx_pcs_lpbk_force lpbk_frce_dis hssi_gen3_rx_pcs_mode hssi_gen3_rx_pcs_mode disable_pcs hssi_gen3_rx_pcs_rate_match_fifo hssi_gen3_rx_pcs_rate_match_fifo bypass_rm_fifo hssi_gen3_rx_pcs_rate_match_fifo_latency hssi_gen3_rx_pcs_rate_match_fifo_latency low_latency hssi_gen3_rx_pcs_reverse_lpbk hssi_gen3_rx_pcs_reverse_lpbk rev_lpbk_dis hssi_gen3_rx_pcs_rx_b4gb_par_lpbk hssi_gen3_rx_pcs_rx_b4gb_par_lpbk b4gb_par_lpbk_dis hssi_gen3_rx_pcs_rx_force_balign hssi_gen3_rx_pcs_rx_force_balign dis_force_balign hssi_gen3_rx_pcs_rx_ins_del_one_skip hssi_gen3_rx_pcs_rx_ins_del_one_skip ins_del_one_skip_dis hssi_gen3_rx_pcs_rx_num_fixed_pat hssi_gen3_rx_pcs_rx_num_fixed_pat 0 hssi_gen3_rx_pcs_rx_test_out_sel hssi_gen3_rx_pcs_rx_test_out_sel rx_test_out0 hssi_gen3_rx_pcs_sup_mode hssi_gen3_rx_pcs_sup_mode user_mode hssi_gen3_rx_pcs_silicon_rev hssi_gen3_rx_pcs_silicon_rev 14nm5bcr2eb hssi_gen3_rx_pcs_reconfig_settings hssi_gen3_rx_pcs_reconfig_settings {} hssi_gen3_tx_pcs_mode hssi_gen3_tx_pcs_mode disable_pcs hssi_gen3_tx_pcs_reverse_lpbk hssi_gen3_tx_pcs_reverse_lpbk rev_lpbk_dis hssi_gen3_tx_pcs_sup_mode hssi_gen3_tx_pcs_sup_mode user_mode hssi_gen3_tx_pcs_tx_bitslip hssi_gen3_tx_pcs_tx_bitslip 0 hssi_gen3_tx_pcs_tx_gbox_byp hssi_gen3_tx_pcs_tx_gbox_byp bypass_gbox hssi_gen3_tx_pcs_silicon_rev hssi_gen3_tx_pcs_silicon_rev 14nm5bcr2eb hssi_gen3_tx_pcs_reconfig_settings hssi_gen3_tx_pcs_reconfig_settings {} hssi_krfec_rx_pcs_blksync_cor_en hssi_krfec_rx_pcs_blksync_cor_en detect hssi_krfec_rx_pcs_bypass_gb hssi_krfec_rx_pcs_bypass_gb bypass_dis hssi_krfec_rx_pcs_clr_ctrl hssi_krfec_rx_pcs_clr_ctrl both_enabled hssi_krfec_rx_pcs_ctrl_bit_reverse hssi_krfec_rx_pcs_ctrl_bit_reverse ctrl_bit_reverse_en hssi_krfec_rx_pcs_data_bit_reverse hssi_krfec_rx_pcs_data_bit_reverse data_bit_reverse_dis hssi_krfec_rx_pcs_dv_start hssi_krfec_rx_pcs_dv_start with_blklock hssi_krfec_rx_pcs_err_mark_type hssi_krfec_rx_pcs_err_mark_type err_mark_10g hssi_krfec_rx_pcs_error_marking_en hssi_krfec_rx_pcs_error_marking_en err_mark_dis hssi_krfec_rx_pcs_low_latency_en hssi_krfec_rx_pcs_low_latency_en disable hssi_krfec_rx_pcs_lpbk_mode hssi_krfec_rx_pcs_lpbk_mode lpbk_dis hssi_krfec_rx_pcs_parity_invalid_enum hssi_krfec_rx_pcs_parity_invalid_enum 8 hssi_krfec_rx_pcs_parity_valid_num hssi_krfec_rx_pcs_parity_valid_num 4 hssi_krfec_rx_pcs_pipeln_blksync hssi_krfec_rx_pcs_pipeln_blksync enable hssi_krfec_rx_pcs_pipeln_descrm hssi_krfec_rx_pcs_pipeln_descrm disable hssi_krfec_rx_pcs_pipeln_errcorrect hssi_krfec_rx_pcs_pipeln_errcorrect disable hssi_krfec_rx_pcs_pipeln_errtrap_ind hssi_krfec_rx_pcs_pipeln_errtrap_ind enable hssi_krfec_rx_pcs_pipeln_errtrap_lfsr hssi_krfec_rx_pcs_pipeln_errtrap_lfsr disable hssi_krfec_rx_pcs_pipeln_errtrap_loc hssi_krfec_rx_pcs_pipeln_errtrap_loc disable hssi_krfec_rx_pcs_pipeln_errtrap_pat hssi_krfec_rx_pcs_pipeln_errtrap_pat disable hssi_krfec_rx_pcs_pipeln_gearbox hssi_krfec_rx_pcs_pipeln_gearbox enable hssi_krfec_rx_pcs_pipeln_syndrm hssi_krfec_rx_pcs_pipeln_syndrm enable hssi_krfec_rx_pcs_pipeln_trans_dec hssi_krfec_rx_pcs_pipeln_trans_dec disable hssi_krfec_rx_pcs_prot_mode hssi_krfec_rx_pcs_prot_mode disable_mode hssi_krfec_rx_pcs_receive_order hssi_krfec_rx_pcs_receive_order receive_lsb hssi_krfec_rx_pcs_rx_testbus_sel hssi_krfec_rx_pcs_rx_testbus_sel overall hssi_krfec_rx_pcs_signal_ok_en hssi_krfec_rx_pcs_signal_ok_en sig_ok_en hssi_krfec_rx_pcs_sup_mode hssi_krfec_rx_pcs_sup_mode user_mode hssi_krfec_rx_pcs_silicon_rev hssi_krfec_rx_pcs_silicon_rev 14nm5bcr2eb hssi_krfec_rx_pcs_reconfig_settings hssi_krfec_rx_pcs_reconfig_settings {} hssi_krfec_tx_pcs_burst_err hssi_krfec_tx_pcs_burst_err burst_err_dis hssi_krfec_tx_pcs_burst_err_len hssi_krfec_tx_pcs_burst_err_len burst_err_len1 hssi_krfec_tx_pcs_ctrl_bit_reverse hssi_krfec_tx_pcs_ctrl_bit_reverse ctrl_bit_reverse_en hssi_krfec_tx_pcs_data_bit_reverse hssi_krfec_tx_pcs_data_bit_reverse data_bit_reverse_dis hssi_krfec_tx_pcs_enc_frame_query hssi_krfec_tx_pcs_enc_frame_query enc_query_dis hssi_krfec_tx_pcs_low_latency_en hssi_krfec_tx_pcs_low_latency_en disable hssi_krfec_tx_pcs_pipeln_encoder hssi_krfec_tx_pcs_pipeln_encoder enable hssi_krfec_tx_pcs_pipeln_scrambler hssi_krfec_tx_pcs_pipeln_scrambler enable hssi_krfec_tx_pcs_prot_mode hssi_krfec_tx_pcs_prot_mode disable_mode hssi_krfec_tx_pcs_sup_mode hssi_krfec_tx_pcs_sup_mode user_mode hssi_krfec_tx_pcs_transcode_err hssi_krfec_tx_pcs_transcode_err trans_err_dis hssi_krfec_tx_pcs_transmit_order hssi_krfec_tx_pcs_transmit_order transmit_lsb hssi_krfec_tx_pcs_tx_testbus_sel hssi_krfec_tx_pcs_tx_testbus_sel overall hssi_krfec_tx_pcs_silicon_rev hssi_krfec_tx_pcs_silicon_rev 14nm5bcr2eb hssi_pipe_gen1_2_elec_idle_delay_val hssi_pipe_gen1_2_elec_idle_delay_val 0 hssi_pipe_gen1_2_error_replace_pad hssi_pipe_gen1_2_error_replace_pad replace_edb hssi_pipe_gen1_2_hip_mode hssi_pipe_gen1_2_hip_mode dis_hip hssi_pipe_gen1_2_ind_error_reporting hssi_pipe_gen1_2_ind_error_reporting dis_ind_error_reporting hssi_pipe_gen1_2_phystatus_delay_val hssi_pipe_gen1_2_phystatus_delay_val 0 hssi_pipe_gen1_2_phystatus_rst_toggle hssi_pipe_gen1_2_phystatus_rst_toggle dis_phystatus_rst_toggle hssi_pipe_gen1_2_pipe_byte_de_serializer_en hssi_pipe_gen1_2_pipe_byte_de_serializer_en dont_care_bds hssi_pipe_gen1_2_prot_mode hssi_pipe_gen1_2_prot_mode disabled_prot_mode hssi_pipe_gen1_2_rpre_emph_a_val hssi_pipe_gen1_2_rpre_emph_a_val 0 hssi_pipe_gen1_2_rpre_emph_b_val hssi_pipe_gen1_2_rpre_emph_b_val 0 hssi_pipe_gen1_2_rpre_emph_c_val hssi_pipe_gen1_2_rpre_emph_c_val 0 hssi_pipe_gen1_2_rpre_emph_d_val hssi_pipe_gen1_2_rpre_emph_d_val 0 hssi_pipe_gen1_2_rpre_emph_e_val hssi_pipe_gen1_2_rpre_emph_e_val 0 hssi_pipe_gen1_2_rvod_sel_a_val hssi_pipe_gen1_2_rvod_sel_a_val 0 hssi_pipe_gen1_2_rvod_sel_b_val hssi_pipe_gen1_2_rvod_sel_b_val 0 hssi_pipe_gen1_2_rvod_sel_c_val hssi_pipe_gen1_2_rvod_sel_c_val 0 hssi_pipe_gen1_2_rvod_sel_d_val hssi_pipe_gen1_2_rvod_sel_d_val 0 hssi_pipe_gen1_2_rvod_sel_e_val hssi_pipe_gen1_2_rvod_sel_e_val 0 hssi_pipe_gen1_2_rx_pipe_enable hssi_pipe_gen1_2_rx_pipe_enable dis_pipe_rx hssi_pipe_gen1_2_rxdetect_bypass hssi_pipe_gen1_2_rxdetect_bypass dis_rxdetect_bypass hssi_pipe_gen1_2_sup_mode hssi_pipe_gen1_2_sup_mode user_mode hssi_pipe_gen1_2_tx_pipe_enable hssi_pipe_gen1_2_tx_pipe_enable dis_pipe_tx hssi_pipe_gen1_2_txswing hssi_pipe_gen1_2_txswing dis_txswing hssi_pipe_gen1_2_silicon_rev hssi_pipe_gen1_2_silicon_rev 14nm5bcr2eb hssi_pipe_gen1_2_reconfig_settings hssi_pipe_gen1_2_reconfig_settings {} hssi_pipe_gen3_bypass_rx_detection_enable hssi_pipe_gen3_bypass_rx_detection_enable false hssi_pipe_gen3_bypass_rx_preset hssi_pipe_gen3_bypass_rx_preset 0 hssi_pipe_gen3_bypass_rx_preset_enable hssi_pipe_gen3_bypass_rx_preset_enable false hssi_pipe_gen3_bypass_tx_coefficent hssi_pipe_gen3_bypass_tx_coefficent 0 hssi_pipe_gen3_bypass_tx_coefficent_enable hssi_pipe_gen3_bypass_tx_coefficent_enable false hssi_pipe_gen3_elecidle_delay_g3 hssi_pipe_gen3_elecidle_delay_g3 0 hssi_pipe_gen3_ind_error_reporting hssi_pipe_gen3_ind_error_reporting dis_ind_error_reporting hssi_pipe_gen3_mode hssi_pipe_gen3_mode disable_pcs hssi_pipe_gen3_phy_status_delay_g12 hssi_pipe_gen3_phy_status_delay_g12 0 hssi_pipe_gen3_phy_status_delay_g3 hssi_pipe_gen3_phy_status_delay_g3 0 hssi_pipe_gen3_phystatus_rst_toggle_g12 hssi_pipe_gen3_phystatus_rst_toggle_g12 dis_phystatus_rst_toggle hssi_pipe_gen3_phystatus_rst_toggle_g3 hssi_pipe_gen3_phystatus_rst_toggle_g3 dis_phystatus_rst_toggle_g3 hssi_pipe_gen3_rate_match_pad_insertion hssi_pipe_gen3_rate_match_pad_insertion dis_rm_fifo_pad_ins hssi_pipe_gen3_sup_mode hssi_pipe_gen3_sup_mode user_mode hssi_pipe_gen3_test_out_sel hssi_pipe_gen3_test_out_sel disable_test_out hssi_pipe_gen3_silicon_rev hssi_pipe_gen3_silicon_rev 14nm5bcr2eb hssi_pipe_gen3_reconfig_settings hssi_pipe_gen3_reconfig_settings {} hssi_pldadapt_rx_aib_clk1_sel hssi_pldadapt_rx_aib_clk1_sel aib_clk1_pld_pma_clkdiv_rx_user hssi_pldadapt_rx_aib_clk2_sel hssi_pldadapt_rx_aib_clk2_sel aib_clk2_pld_pcs_rx_clk_out hssi_pldadapt_rx_hdpldadapt_aib_fabric_pld_pma_hclk_hz hssi_pldadapt_rx_hdpldadapt_aib_fabric_pld_pma_hclk_hz 0 hssi_pldadapt_rx_hdpldadapt_aib_fabric_rx_sr_clk_in_hz hssi_pldadapt_rx_hdpldadapt_aib_fabric_rx_sr_clk_in_hz 0 hssi_pldadapt_rx_hdpldadapt_aib_fabric_rx_transfer_clk_hz hssi_pldadapt_rx_hdpldadapt_aib_fabric_rx_transfer_clk_hz 322265624 hssi_pldadapt_rx_asn_bypass_pma_pcie_sw_done hssi_pldadapt_rx_asn_bypass_pma_pcie_sw_done disable hssi_pldadapt_rx_asn_en hssi_pldadapt_rx_asn_en disable hssi_pldadapt_rx_asn_wait_for_dll_reset_cnt hssi_pldadapt_rx_asn_wait_for_dll_reset_cnt 64 hssi_pldadapt_rx_asn_wait_for_fifo_flush_cnt hssi_pldadapt_rx_asn_wait_for_fifo_flush_cnt 64 hssi_pldadapt_rx_asn_wait_for_pma_pcie_sw_done_cnt hssi_pldadapt_rx_asn_wait_for_pma_pcie_sw_done_cnt 64 hssi_pldadapt_rx_bonding_dft_en hssi_pldadapt_rx_bonding_dft_en dft_dis hssi_pldadapt_rx_bonding_dft_val hssi_pldadapt_rx_bonding_dft_val dft_0 hssi_pldadapt_rx_chnl_bonding hssi_pldadapt_rx_chnl_bonding disable hssi_pldadapt_rx_clock_del_measure_enable hssi_pldadapt_rx_clock_del_measure_enable disable hssi_pldadapt_rx_comp_cnt hssi_pldadapt_rx_comp_cnt 0 hssi_pldadapt_rx_compin_sel hssi_pldadapt_rx_compin_sel compin_master hssi_pldadapt_rx_hdpldadapt_csr_clk_hz hssi_pldadapt_rx_hdpldadapt_csr_clk_hz 0 hssi_pldadapt_rx_ctrl_plane_bonding hssi_pldadapt_rx_ctrl_plane_bonding individual hssi_pldadapt_rx_ds_bypass_pipeln hssi_pldadapt_rx_ds_bypass_pipeln ds_bypass_pipeln_dis hssi_pldadapt_rx_ds_last_chnl hssi_pldadapt_rx_ds_last_chnl ds_last_chnl hssi_pldadapt_rx_ds_master hssi_pldadapt_rx_ds_master ds_master_en hssi_pldadapt_rx_duplex_mode hssi_pldadapt_rx_duplex_mode enable hssi_pldadapt_rx_dv_mode hssi_pldadapt_rx_dv_mode dv_mode_en hssi_pldadapt_rx_fifo_double_read hssi_pldadapt_rx_fifo_double_read fifo_double_read_en hssi_pldadapt_rx_fifo_mode hssi_pldadapt_rx_fifo_mode generic_basic hssi_pldadapt_rx_fifo_rd_clk_ins_sm_scg_en hssi_pldadapt_rx_fifo_rd_clk_ins_sm_scg_en enable hssi_pldadapt_rx_fifo_rd_clk_scg_en hssi_pldadapt_rx_fifo_rd_clk_scg_en disable hssi_pldadapt_rx_fifo_rd_clk_sel hssi_pldadapt_rx_fifo_rd_clk_sel fifo_rd_clk_pld_rx_clk1 hssi_pldadapt_rx_fifo_stop_rd hssi_pldadapt_rx_fifo_stop_rd n_rd_empty hssi_pldadapt_rx_fifo_stop_wr hssi_pldadapt_rx_fifo_stop_wr n_wr_full hssi_pldadapt_rx_fifo_width hssi_pldadapt_rx_fifo_width fifo_double_width hssi_pldadapt_rx_fifo_wr_clk_del_sm_scg_en hssi_pldadapt_rx_fifo_wr_clk_del_sm_scg_en enable hssi_pldadapt_rx_fifo_wr_clk_scg_en hssi_pldadapt_rx_fifo_wr_clk_scg_en disable hssi_pldadapt_rx_fifo_wr_clk_sel hssi_pldadapt_rx_fifo_wr_clk_sel fifo_wr_clk_rx_transfer_clk hssi_pldadapt_rx_free_run_div_clk hssi_pldadapt_rx_free_run_div_clk out_of_reset_sync hssi_pldadapt_rx_fsr_pld_10g_rx_crc32_err_rst_val hssi_pldadapt_rx_fsr_pld_10g_rx_crc32_err_rst_val reset_to_zero_crc32 hssi_pldadapt_rx_fsr_pld_8g_sigdet_out_rst_val hssi_pldadapt_rx_fsr_pld_8g_sigdet_out_rst_val reset_to_zero_sigdet hssi_pldadapt_rx_fsr_pld_ltd_b_rst_val hssi_pldadapt_rx_fsr_pld_ltd_b_rst_val reset_to_one_ltdb hssi_pldadapt_rx_fsr_pld_ltr_rst_val hssi_pldadapt_rx_fsr_pld_ltr_rst_val reset_to_zero_ltr hssi_pldadapt_rx_fsr_pld_rx_fifo_align_clr_rst_val hssi_pldadapt_rx_fsr_pld_rx_fifo_align_clr_rst_val reset_to_zero_alignclr hssi_pldadapt_rx_gb_rx_idwidth hssi_pldadapt_rx_gb_rx_idwidth idwidth_64 hssi_pldadapt_rx_gb_rx_odwidth hssi_pldadapt_rx_gb_rx_odwidth odwidth_66 hssi_pldadapt_rx_hip_mode hssi_pldadapt_rx_hip_mode disable_hip hssi_pldadapt_rx_hrdrst_align_bypass hssi_pldadapt_rx_hrdrst_align_bypass enable hssi_pldadapt_rx_hrdrst_dll_lock_bypass hssi_pldadapt_rx_hrdrst_dll_lock_bypass disable hssi_pldadapt_rx_hrdrst_rst_sm_dis hssi_pldadapt_rx_hrdrst_rst_sm_dis enable_rx_rst_sm hssi_pldadapt_rx_hrdrst_rx_osc_clk_scg_en hssi_pldadapt_rx_hrdrst_rx_osc_clk_scg_en disable hssi_pldadapt_rx_hrdrst_user_ctl_en hssi_pldadapt_rx_hrdrst_user_ctl_en disable hssi_pldadapt_rx_indv hssi_pldadapt_rx_indv indv_en hssi_pldadapt_rx_internal_clk1_sel1 hssi_pldadapt_rx_internal_clk1_sel1 pma_clks_or_txfiford_post_ct_mux_clk1_mux1 hssi_pldadapt_rx_internal_clk1_sel2 hssi_pldadapt_rx_internal_clk1_sel2 pma_clks_clk1_mux2 hssi_pldadapt_rx_internal_clk2_sel1 hssi_pldadapt_rx_internal_clk2_sel1 pma_clks_or_rxfifowr_post_ct_mux_clk2_mux1 hssi_pldadapt_rx_internal_clk2_sel2 hssi_pldadapt_rx_internal_clk2_sel2 pma_clks_clk2_mux2 hssi_pldadapt_rx_loopback_mode hssi_pldadapt_rx_loopback_mode disable hssi_pldadapt_rx_low_latency_en hssi_pldadapt_rx_low_latency_en disable hssi_pldadapt_rx_lpbk_mode hssi_pldadapt_rx_lpbk_mode disable hssi_pldadapt_rx_osc_clk_scg_en hssi_pldadapt_rx_osc_clk_scg_en disable hssi_pldadapt_rx_phcomp_rd_del hssi_pldadapt_rx_phcomp_rd_del phcomp_rd_del2 hssi_pldadapt_rx_pipe_enable hssi_pldadapt_rx_pipe_enable disable hssi_pldadapt_rx_pipe_mode hssi_pldadapt_rx_pipe_mode disable_pipe hssi_pldadapt_rx_hdpldadapt_pld_avmm1_clk_rowclk_hz hssi_pldadapt_rx_hdpldadapt_pld_avmm1_clk_rowclk_hz 0 hssi_pldadapt_rx_hdpldadapt_pld_avmm2_clk_rowclk_hz hssi_pldadapt_rx_hdpldadapt_pld_avmm2_clk_rowclk_hz 0 hssi_pldadapt_rx_pld_clk1_delay_en hssi_pldadapt_rx_pld_clk1_delay_en enable hssi_pldadapt_rx_pld_clk1_delay_sel hssi_pldadapt_rx_pld_clk1_delay_sel delay_path13 hssi_pldadapt_rx_pld_clk1_inv_en hssi_pldadapt_rx_pld_clk1_inv_en disable hssi_pldadapt_rx_pld_clk1_sel hssi_pldadapt_rx_pld_clk1_sel pld_clk1_dcm hssi_pldadapt_rx_hdpldadapt_pld_rx_clk1_dcm_hz hssi_pldadapt_rx_hdpldadapt_pld_rx_clk1_dcm_hz 156250000 hssi_pldadapt_rx_hdpldadapt_pld_rx_clk1_rowclk_hz hssi_pldadapt_rx_hdpldadapt_pld_rx_clk1_rowclk_hz 156250000 hssi_pldadapt_rx_hdpldadapt_pld_sclk1_rowclk_hz hssi_pldadapt_rx_hdpldadapt_pld_sclk1_rowclk_hz 0 hssi_pldadapt_rx_hdpldadapt_pld_sclk2_rowclk_hz hssi_pldadapt_rx_hdpldadapt_pld_sclk2_rowclk_hz 0 hssi_pldadapt_rx_pma_hclk_scg_en hssi_pldadapt_rx_pma_hclk_scg_en enable hssi_pldadapt_rx_powerdown_mode hssi_pldadapt_rx_powerdown_mode powerup hssi_pldadapt_rx_powermode_dc hssi_pldadapt_rx_powermode_dc powerdown hssi_pldadapt_rx_powermode_freq_hz_aib_fabric_rx_sr_clk_in hssi_pldadapt_rx_powermode_freq_hz_aib_fabric_rx_sr_clk_in 0 hssi_pldadapt_rx_powermode_freq_hz_pld_rx_clk1_dcm hssi_pldadapt_rx_powermode_freq_hz_pld_rx_clk1_dcm 0 hssi_pldadapt_rx_rx_datapath_tb_sel hssi_pldadapt_rx_rx_datapath_tb_sel cp_bond hssi_pldadapt_rx_rx_fastbond_rden hssi_pldadapt_rx_rx_fastbond_rden rden_ds_fast_us_fast hssi_pldadapt_rx_rx_fastbond_wren hssi_pldadapt_rx_rx_fastbond_wren wren_ds_del_us_del hssi_pldadapt_rx_rx_fifo_power_mode hssi_pldadapt_rx_rx_fifo_power_mode full_width_full_depth hssi_pldadapt_rx_rx_fifo_read_latency_adjust hssi_pldadapt_rx_rx_fifo_read_latency_adjust disable hssi_pldadapt_rx_rx_fifo_write_ctrl hssi_pldadapt_rx_rx_fifo_write_ctrl blklock_ignore hssi_pldadapt_rx_rx_fifo_write_latency_adjust hssi_pldadapt_rx_rx_fifo_write_latency_adjust disable hssi_pldadapt_rx_rx_osc_clock_setting hssi_pldadapt_rx_rx_osc_clock_setting osc_clk_div_by1 hssi_pldadapt_rx_rx_pld_8g_eidleinfersel_polling_bypass hssi_pldadapt_rx_rx_pld_8g_eidleinfersel_polling_bypass disable hssi_pldadapt_rx_rx_pld_pma_eye_monitor_polling_bypass hssi_pldadapt_rx_rx_pld_pma_eye_monitor_polling_bypass disable hssi_pldadapt_rx_rx_pld_pma_pcie_switch_polling_bypass hssi_pldadapt_rx_rx_pld_pma_pcie_switch_polling_bypass disable hssi_pldadapt_rx_rx_pld_pma_reser_out_polling_bypass hssi_pldadapt_rx_rx_pld_pma_reser_out_polling_bypass disable hssi_pldadapt_rx_rx_prbs_flags_sr_enable hssi_pldadapt_rx_rx_prbs_flags_sr_enable disable hssi_pldadapt_rx_rx_true_b2b hssi_pldadapt_rx_rx_true_b2b b2b hssi_pldadapt_rx_rx_usertest_sel hssi_pldadapt_rx_rx_usertest_sel enable hssi_pldadapt_rx_rxfifo_empty hssi_pldadapt_rx_rxfifo_empty empty_dw hssi_pldadapt_rx_rxfifo_full hssi_pldadapt_rx_rxfifo_full full_non_pc_dw hssi_pldadapt_rx_rxfifo_mode hssi_pldadapt_rx_rxfifo_mode rxgeneric_basic hssi_pldadapt_rx_rxfifo_pempty hssi_pldadapt_rx_rxfifo_pempty 4 hssi_pldadapt_rx_rxfifo_pfull hssi_pldadapt_rx_rxfifo_pfull 50 hssi_pldadapt_rx_rxfiford_post_ct_sel hssi_pldadapt_rx_rxfiford_post_ct_sel rxfiford_sclk_post_ct hssi_pldadapt_rx_rxfifowr_post_ct_sel hssi_pldadapt_rx_rxfifowr_post_ct_sel rxfifowr_sclk_post_ct hssi_pldadapt_rx_sclk_sel hssi_pldadapt_rx_sclk_sel sclk1_rowclk hssi_pldadapt_rx_hdpldadapt_speed_grade hssi_pldadapt_rx_hdpldadapt_speed_grade dash_2 hssi_pldadapt_rx_hdpldadapt_sr_sr_testbus_sel hssi_pldadapt_rx_hdpldadapt_sr_sr_testbus_sel ssr_testbus hssi_pldadapt_rx_stretch_num_stages hssi_pldadapt_rx_stretch_num_stages two_stage hssi_pldadapt_rx_sup_mode hssi_pldadapt_rx_sup_mode user_mode hssi_pldadapt_rx_txfiford_post_ct_sel hssi_pldadapt_rx_txfiford_post_ct_sel txfiford_sclk_post_ct hssi_pldadapt_rx_txfifowr_post_ct_sel hssi_pldadapt_rx_txfifowr_post_ct_sel txfifowr_sclk_post_ct hssi_pldadapt_rx_us_bypass_pipeln hssi_pldadapt_rx_us_bypass_pipeln us_bypass_pipeln_dis hssi_pldadapt_rx_us_last_chnl hssi_pldadapt_rx_us_last_chnl us_last_chnl hssi_pldadapt_rx_us_master hssi_pldadapt_rx_us_master us_master_en hssi_pldadapt_rx_word_align hssi_pldadapt_rx_word_align wa_en hssi_pldadapt_rx_word_align_enable hssi_pldadapt_rx_word_align_enable enable hssi_pldadapt_rx_silicon_rev hssi_pldadapt_rx_silicon_rev 14nm5bcr2eb hssi_pldadapt_rx_reconfig_settings hssi_pldadapt_rx_reconfig_settings {} hssi_pldadapt_tx_aib_clk1_sel hssi_pldadapt_tx_aib_clk1_sel aib_clk1_pld_pma_clkdiv_tx_user hssi_pldadapt_tx_aib_clk2_sel hssi_pldadapt_tx_aib_clk2_sel aib_clk2_pld_pcs_tx_clk_out hssi_pldadapt_tx_hdpldadapt_aib_fabric_pld_pma_hclk_hz hssi_pldadapt_tx_hdpldadapt_aib_fabric_pld_pma_hclk_hz 0 hssi_pldadapt_tx_hdpldadapt_aib_fabric_pma_aib_tx_clk_hz hssi_pldadapt_tx_hdpldadapt_aib_fabric_pma_aib_tx_clk_hz 322265625 hssi_pldadapt_tx_hdpldadapt_aib_fabric_tx_sr_clk_in_hz hssi_pldadapt_tx_hdpldadapt_aib_fabric_tx_sr_clk_in_hz 0 hssi_pldadapt_tx_bonding_dft_en hssi_pldadapt_tx_bonding_dft_en dft_dis hssi_pldadapt_tx_bonding_dft_val hssi_pldadapt_tx_bonding_dft_val dft_0 hssi_pldadapt_tx_chnl_bonding hssi_pldadapt_tx_chnl_bonding disable hssi_pldadapt_tx_comp_cnt hssi_pldadapt_tx_comp_cnt 0 hssi_pldadapt_tx_compin_sel hssi_pldadapt_tx_compin_sel compin_master hssi_pldadapt_tx_hdpldadapt_csr_clk_hz hssi_pldadapt_tx_hdpldadapt_csr_clk_hz 0 hssi_pldadapt_tx_ctrl_plane_bonding hssi_pldadapt_tx_ctrl_plane_bonding individual hssi_pldadapt_tx_ds_bypass_pipeln hssi_pldadapt_tx_ds_bypass_pipeln ds_bypass_pipeln_dis hssi_pldadapt_tx_ds_last_chnl hssi_pldadapt_tx_ds_last_chnl ds_last_chnl hssi_pldadapt_tx_ds_master hssi_pldadapt_tx_ds_master ds_master_en hssi_pldadapt_tx_duplex_mode hssi_pldadapt_tx_duplex_mode enable hssi_pldadapt_tx_dv_bond hssi_pldadapt_tx_dv_bond dv_bond_dis hssi_pldadapt_tx_dv_gen hssi_pldadapt_tx_dv_gen dv_gen_en hssi_pldadapt_tx_fifo_double_write hssi_pldadapt_tx_fifo_double_write fifo_double_write_en hssi_pldadapt_tx_fifo_mode hssi_pldadapt_tx_fifo_mode generic_basic hssi_pldadapt_tx_fifo_rd_clk_frm_gen_scg_en hssi_pldadapt_tx_fifo_rd_clk_frm_gen_scg_en enable hssi_pldadapt_tx_fifo_rd_clk_scg_en hssi_pldadapt_tx_fifo_rd_clk_scg_en disable hssi_pldadapt_tx_fifo_rd_clk_sel hssi_pldadapt_tx_fifo_rd_clk_sel fifo_rd_pma_aib_tx_clk hssi_pldadapt_tx_fifo_stop_rd hssi_pldadapt_tx_fifo_stop_rd n_rd_empty hssi_pldadapt_tx_fifo_stop_wr hssi_pldadapt_tx_fifo_stop_wr n_wr_full hssi_pldadapt_tx_fifo_width hssi_pldadapt_tx_fifo_width fifo_double_width hssi_pldadapt_tx_fifo_wr_clk_scg_en hssi_pldadapt_tx_fifo_wr_clk_scg_en disable hssi_pldadapt_tx_fpll_shared_direct_async_in_sel hssi_pldadapt_tx_fpll_shared_direct_async_in_sel fpll_shared_direct_async_in_rowclk hssi_pldadapt_tx_frmgen_burst hssi_pldadapt_tx_frmgen_burst frmgen_burst_dis hssi_pldadapt_tx_frmgen_bypass hssi_pldadapt_tx_frmgen_bypass frmgen_bypass_en hssi_pldadapt_tx_frmgen_mfrm_length hssi_pldadapt_tx_frmgen_mfrm_length 2048 hssi_pldadapt_tx_frmgen_pipeln hssi_pldadapt_tx_frmgen_pipeln frmgen_pipeln_en hssi_pldadapt_tx_frmgen_pyld_ins hssi_pldadapt_tx_frmgen_pyld_ins frmgen_pyld_ins_dis hssi_pldadapt_tx_frmgen_wordslip hssi_pldadapt_tx_frmgen_wordslip frmgen_wordslip_dis hssi_pldadapt_tx_fsr_hip_fsr_in_bit0_rst_val hssi_pldadapt_tx_fsr_hip_fsr_in_bit0_rst_val reset_to_one_hfsrin0 hssi_pldadapt_tx_fsr_hip_fsr_in_bit1_rst_val hssi_pldadapt_tx_fsr_hip_fsr_in_bit1_rst_val reset_to_one_hfsrin1 hssi_pldadapt_tx_fsr_hip_fsr_in_bit2_rst_val hssi_pldadapt_tx_fsr_hip_fsr_in_bit2_rst_val reset_to_one_hfsrin2 hssi_pldadapt_tx_fsr_hip_fsr_in_bit3_rst_val hssi_pldadapt_tx_fsr_hip_fsr_in_bit3_rst_val reset_to_zero_hfsrin3 hssi_pldadapt_tx_fsr_hip_fsr_out_bit0_rst_val hssi_pldadapt_tx_fsr_hip_fsr_out_bit0_rst_val reset_to_one_hfsrout0 hssi_pldadapt_tx_fsr_hip_fsr_out_bit1_rst_val hssi_pldadapt_tx_fsr_hip_fsr_out_bit1_rst_val reset_to_one_hfsrout1 hssi_pldadapt_tx_fsr_hip_fsr_out_bit2_rst_val hssi_pldadapt_tx_fsr_hip_fsr_out_bit2_rst_val reset_to_zero_hfsrout2 hssi_pldadapt_tx_fsr_hip_fsr_out_bit3_rst_val hssi_pldadapt_tx_fsr_hip_fsr_out_bit3_rst_val reset_to_zero_hfsrout3 hssi_pldadapt_tx_fsr_mask_tx_pll_rst_val hssi_pldadapt_tx_fsr_mask_tx_pll_rst_val reset_to_zero_maskpll hssi_pldadapt_tx_fsr_pld_txelecidle_rst_val hssi_pldadapt_tx_fsr_pld_txelecidle_rst_val reset_to_zero_txelec hssi_pldadapt_tx_gb_tx_idwidth hssi_pldadapt_tx_gb_tx_idwidth idwidth_66 hssi_pldadapt_tx_gb_tx_odwidth hssi_pldadapt_tx_gb_tx_odwidth odwidth_64 hssi_pldadapt_tx_hip_mode hssi_pldadapt_tx_hip_mode disable_hip hssi_pldadapt_tx_hip_osc_clk_scg_en hssi_pldadapt_tx_hip_osc_clk_scg_en enable hssi_pldadapt_tx_hrdrst_dcd_cal_done_bypass hssi_pldadapt_tx_hrdrst_dcd_cal_done_bypass disable hssi_pldadapt_tx_hrdrst_rst_sm_dis hssi_pldadapt_tx_hrdrst_rst_sm_dis enable_tx_rst_sm hssi_pldadapt_tx_hrdrst_rx_osc_clk_scg_en hssi_pldadapt_tx_hrdrst_rx_osc_clk_scg_en disable hssi_pldadapt_tx_hrdrst_user_ctl_en hssi_pldadapt_tx_hrdrst_user_ctl_en disable hssi_pldadapt_tx_indv hssi_pldadapt_tx_indv indv_en hssi_pldadapt_tx_loopback_mode hssi_pldadapt_tx_loopback_mode disable hssi_pldadapt_tx_low_latency_en hssi_pldadapt_tx_low_latency_en disable hssi_pldadapt_tx_osc_clk_scg_en hssi_pldadapt_tx_osc_clk_scg_en disable hssi_pldadapt_tx_phcomp_rd_del hssi_pldadapt_tx_phcomp_rd_del phcomp_rd_del2 hssi_pldadapt_tx_pipe_mode hssi_pldadapt_tx_pipe_mode disable_pipe hssi_pldadapt_tx_hdpldadapt_pld_avmm1_clk_rowclk_hz hssi_pldadapt_tx_hdpldadapt_pld_avmm1_clk_rowclk_hz 0 hssi_pldadapt_tx_hdpldadapt_pld_avmm2_clk_rowclk_hz hssi_pldadapt_tx_hdpldadapt_pld_avmm2_clk_rowclk_hz 0 hssi_pldadapt_tx_pld_clk1_delay_en hssi_pldadapt_tx_pld_clk1_delay_en enable hssi_pldadapt_tx_pld_clk1_delay_sel hssi_pldadapt_tx_pld_clk1_delay_sel delay_path15 hssi_pldadapt_tx_pld_clk1_inv_en hssi_pldadapt_tx_pld_clk1_inv_en disable hssi_pldadapt_tx_pld_clk1_sel hssi_pldadapt_tx_pld_clk1_sel pld_clk1_dcm hssi_pldadapt_tx_pld_clk2_sel hssi_pldadapt_tx_pld_clk2_sel pld_clk2_dcm hssi_pldadapt_tx_hdpldadapt_pld_sclk1_rowclk_hz hssi_pldadapt_tx_hdpldadapt_pld_sclk1_rowclk_hz 0 hssi_pldadapt_tx_hdpldadapt_pld_sclk2_rowclk_hz hssi_pldadapt_tx_hdpldadapt_pld_sclk2_rowclk_hz 0 hssi_pldadapt_tx_hdpldadapt_pld_tx_clk1_dcm_hz hssi_pldadapt_tx_hdpldadapt_pld_tx_clk1_dcm_hz 156250000 hssi_pldadapt_tx_hdpldadapt_pld_tx_clk1_rowclk_hz hssi_pldadapt_tx_hdpldadapt_pld_tx_clk1_rowclk_hz 156250000 hssi_pldadapt_tx_hdpldadapt_pld_tx_clk2_dcm_hz hssi_pldadapt_tx_hdpldadapt_pld_tx_clk2_dcm_hz 322265624 hssi_pldadapt_tx_hdpldadapt_pld_tx_clk2_rowclk_hz hssi_pldadapt_tx_hdpldadapt_pld_tx_clk2_rowclk_hz 322265624 hssi_pldadapt_tx_pma_aib_tx_clk_expected_setting hssi_pldadapt_tx_pma_aib_tx_clk_expected_setting x2 hssi_pldadapt_tx_powerdown_mode hssi_pldadapt_tx_powerdown_mode powerup hssi_pldadapt_tx_powermode_dc hssi_pldadapt_tx_powermode_dc powerdown hssi_pldadapt_tx_powermode_freq_hz_aib_fabric_rx_sr_clk_in hssi_pldadapt_tx_powermode_freq_hz_aib_fabric_rx_sr_clk_in 0 hssi_pldadapt_tx_powermode_freq_hz_pld_tx_clk1_dcm hssi_pldadapt_tx_powermode_freq_hz_pld_tx_clk1_dcm 0 hssi_pldadapt_tx_sh_err hssi_pldadapt_tx_sh_err sh_err_dis hssi_pldadapt_tx_hdpldadapt_speed_grade hssi_pldadapt_tx_hdpldadapt_speed_grade dash_2 hssi_pldadapt_tx_hdpldadapt_sr_sr_testbus_sel hssi_pldadapt_tx_hdpldadapt_sr_sr_testbus_sel ssr_testbus hssi_pldadapt_tx_stretch_num_stages hssi_pldadapt_tx_stretch_num_stages two_stage hssi_pldadapt_tx_sup_mode hssi_pldadapt_tx_sup_mode user_mode hssi_pldadapt_tx_tx_datapath_tb_sel hssi_pldadapt_tx_tx_datapath_tb_sel cp_bond hssi_pldadapt_tx_tx_fastbond_rden hssi_pldadapt_tx_tx_fastbond_rden rden_ds_fast_us_fast hssi_pldadapt_tx_tx_fastbond_wren hssi_pldadapt_tx_tx_fastbond_wren wren_ds_fast_us_fast hssi_pldadapt_tx_tx_fifo_power_mode hssi_pldadapt_tx_tx_fifo_power_mode full_width_full_depth hssi_pldadapt_tx_tx_fifo_read_latency_adjust hssi_pldadapt_tx_tx_fifo_read_latency_adjust disable hssi_pldadapt_tx_tx_fifo_write_latency_adjust hssi_pldadapt_tx_tx_fifo_write_latency_adjust disable hssi_pldadapt_tx_tx_hip_aib_ssr_in_polling_bypass hssi_pldadapt_tx_tx_hip_aib_ssr_in_polling_bypass disable hssi_pldadapt_tx_tx_osc_clock_setting hssi_pldadapt_tx_tx_osc_clock_setting osc_clk_div_by1 hssi_pldadapt_tx_tx_pld_10g_tx_bitslip_polling_bypass hssi_pldadapt_tx_tx_pld_10g_tx_bitslip_polling_bypass disable hssi_pldadapt_tx_tx_pld_8g_tx_boundary_sel_polling_bypass hssi_pldadapt_tx_tx_pld_8g_tx_boundary_sel_polling_bypass disable hssi_pldadapt_tx_tx_pld_pma_fpll_cnt_sel_polling_bypass hssi_pldadapt_tx_tx_pld_pma_fpll_cnt_sel_polling_bypass disable hssi_pldadapt_tx_tx_pld_pma_fpll_num_phase_shifts_polling_bypass hssi_pldadapt_tx_tx_pld_pma_fpll_num_phase_shifts_polling_bypass disable hssi_pldadapt_tx_tx_usertest_sel hssi_pldadapt_tx_tx_usertest_sel enable hssi_pldadapt_tx_txfifo_empty hssi_pldadapt_tx_txfifo_empty empty_default hssi_pldadapt_tx_txfifo_full hssi_pldadapt_tx_txfifo_full full_non_pc_dw hssi_pldadapt_tx_txfifo_mode hssi_pldadapt_tx_txfifo_mode txgeneric_basic hssi_pldadapt_tx_txfifo_pempty hssi_pldadapt_tx_txfifo_pempty 2 hssi_pldadapt_tx_txfifo_pfull hssi_pldadapt_tx_txfifo_pfull 18 hssi_pldadapt_tx_us_bypass_pipeln hssi_pldadapt_tx_us_bypass_pipeln us_bypass_pipeln_dis hssi_pldadapt_tx_us_last_chnl hssi_pldadapt_tx_us_last_chnl us_last_chnl hssi_pldadapt_tx_us_master hssi_pldadapt_tx_us_master us_master_en hssi_pldadapt_tx_word_align_enable hssi_pldadapt_tx_word_align_enable enable hssi_pldadapt_tx_word_mark hssi_pldadapt_tx_word_mark wm_en hssi_pldadapt_tx_silicon_rev hssi_pldadapt_tx_silicon_rev 14nm5bcr2eb hssi_pldadapt_tx_reconfig_settings hssi_pldadapt_tx_reconfig_settings {} pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch0_src pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch0_src cdr_clkin_scratch0_src_refclk_iqclk pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch1_src pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch1_src cdr_clkin_scratch1_src_refclk_iqclk pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch2_src pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch2_src cdr_clkin_scratch2_src_refclk_iqclk pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch3_src pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch3_src cdr_clkin_scratch3_src_refclk_iqclk pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch4_src pma_cdr_refclk_pm_cr_tx_rx_cdr_clkin_scratch4_src cdr_clkin_scratch4_src_refclk_iqclk pma_cdr_refclk_powerdown_mode pma_cdr_refclk_powerdown_mode powerup pma_cdr_refclk_receiver_detect_src pma_cdr_refclk_receiver_detect_src iqclk_src pma_cdr_refclk_pm_cr_tx_rx_scratch0_src pma_cdr_refclk_pm_cr_tx_rx_scratch0_src scratch0_power_down pma_cdr_refclk_pm_cr_tx_rx_scratch1_src pma_cdr_refclk_pm_cr_tx_rx_scratch1_src scratch1_power_down pma_cdr_refclk_pm_cr_tx_rx_scratch2_src pma_cdr_refclk_pm_cr_tx_rx_scratch2_src scratch2_power_down pma_cdr_refclk_pm_cr_tx_rx_scratch3_src pma_cdr_refclk_pm_cr_tx_rx_scratch3_src scratch3_power_down pma_cdr_refclk_pm_cr_tx_rx_scratch4_src pma_cdr_refclk_pm_cr_tx_rx_scratch4_src scratch4_power_down pma_cdr_refclk_xmux_refclk_src pma_cdr_refclk_xmux_refclk_src refclk_iqclk pma_cdr_refclk_xpm_iqref_mux_iqclk_sel pma_cdr_refclk_xpm_iqref_mux_iqclk_sel power_down pma_cdr_refclk_silicon_rev pma_cdr_refclk_silicon_rev 14nm5bcr2eb pma_cdr_refclk_refclk_select pma_cdr_refclk_refclk_select ref_iqclk0 pma_cdr_refclk_inclk0_logical_to_physical_mapping pma_cdr_refclk_inclk0_logical_to_physical_mapping ref_iqclk0 pma_cdr_refclk_inclk1_logical_to_physical_mapping pma_cdr_refclk_inclk1_logical_to_physical_mapping ref_iqclk0 pma_cdr_refclk_inclk2_logical_to_physical_mapping pma_cdr_refclk_inclk2_logical_to_physical_mapping ref_iqclk0 pma_cdr_refclk_inclk3_logical_to_physical_mapping pma_cdr_refclk_inclk3_logical_to_physical_mapping ref_iqclk0 pma_cdr_refclk_inclk4_logical_to_physical_mapping pma_cdr_refclk_inclk4_logical_to_physical_mapping ref_iqclk0 hssi_rx_pcs_pma_interface_block_sel hssi_rx_pcs_pma_interface_block_sel ten_g_pcs hssi_rx_pcs_pma_interface_channel_operation_mode hssi_rx_pcs_pma_interface_channel_operation_mode tx_rx_pair_enabled hssi_rx_pcs_pma_interface_clkslip_sel hssi_rx_pcs_pma_interface_clkslip_sel pld hssi_rx_pcs_pma_interface_lpbk_en hssi_rx_pcs_pma_interface_lpbk_en disable hssi_rx_pcs_pma_interface_master_clk_sel hssi_rx_pcs_pma_interface_master_clk_sel master_rx_pma_clk hssi_rx_pcs_pma_interface_pldif_datawidth_mode hssi_rx_pcs_pma_interface_pldif_datawidth_mode pldif_data_10bit hssi_rx_pcs_pma_interface_pma_dw_rx hssi_rx_pcs_pma_interface_pma_dw_rx pma_64b_rx hssi_rx_pcs_pma_interface_pma_if_dft_en hssi_rx_pcs_pma_interface_pma_if_dft_en dft_dis hssi_rx_pcs_pma_interface_pma_if_dft_val hssi_rx_pcs_pma_interface_pma_if_dft_val dft_0 hssi_rx_pcs_pma_interface_prbs9_dwidth hssi_rx_pcs_pma_interface_prbs9_dwidth prbs9_64b hssi_rx_pcs_pma_interface_prbs_clken hssi_rx_pcs_pma_interface_prbs_clken prbs_clk_dis hssi_rx_pcs_pma_interface_prbs_ver hssi_rx_pcs_pma_interface_prbs_ver prbs_off hssi_rx_pcs_pma_interface_prot_mode_rx hssi_rx_pcs_pma_interface_prot_mode_rx teng_basic_mode_rx hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion rx_dyn_polinv_dis hssi_rx_pcs_pma_interface_rx_lpbk_en hssi_rx_pcs_pma_interface_rx_lpbk_en lpbk_dis hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok force_sig_ok hssi_rx_pcs_pma_interface_rx_prbs_mask hssi_rx_pcs_pma_interface_rx_prbs_mask prbsmask128 hssi_rx_pcs_pma_interface_rx_prbs_mode hssi_rx_pcs_pma_interface_rx_prbs_mode teng_mode hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel sel_sig_det hssi_rx_pcs_pma_interface_rx_static_polarity_inversion hssi_rx_pcs_pma_interface_rx_static_polarity_inversion rx_stat_polinv_dis hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en uhsif_lpbk_dis hssi_rx_pcs_pma_interface_sup_mode hssi_rx_pcs_pma_interface_sup_mode user_mode hssi_rx_pcs_pma_interface_silicon_rev hssi_rx_pcs_pma_interface_silicon_rev 14nm5bcr2eb hssi_rx_pcs_pma_interface_reconfig_settings hssi_rx_pcs_pma_interface_reconfig_settings {} hssi_rx_pld_pcs_interface_hd_pcs10g_advanced_user_mode_rx hssi_rx_pld_pcs_interface_hd_pcs10g_advanced_user_mode_rx disable hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode tx_rx_pair_enabled hssi_rx_pld_pcs_interface_hd_pcs10g_channel_operation_mode hssi_rx_pld_pcs_interface_hd_pcs10g_channel_operation_mode tx_rx_pair_enabled hssi_rx_pld_pcs_interface_hd_pcs8g_channel_operation_mode hssi_rx_pld_pcs_interface_hd_pcs8g_channel_operation_mode tx_rx_pair_enabled hssi_rx_pld_pcs_interface_hd_pcs_channel_channel_operation_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_channel_operation_mode tx_rx_pair_enabled hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_channel_operation_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_channel_operation_mode tx_rx_pair_enabled hssi_rx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_channel_operation_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_channel_operation_mode tx_rx_pair_enabled hssi_rx_pld_pcs_interface_hd_pcs_channel_clklow_clk_hz hssi_rx_pld_pcs_interface_hd_pcs_channel_clklow_clk_hz 322265625 hssi_rx_pld_pcs_interface_hd_pcs10g_ctrl_plane_bonding_rx hssi_rx_pld_pcs_interface_hd_pcs10g_ctrl_plane_bonding_rx individual_rx hssi_rx_pld_pcs_interface_hd_pcs8g_ctrl_plane_bonding_rx hssi_rx_pld_pcs_interface_hd_pcs8g_ctrl_plane_bonding_rx individual_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_ctrl_plane_bonding_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_ctrl_plane_bonding_rx individual_rx hssi_rx_pld_pcs_interface_hd_pcs10g_fifo_mode_rx hssi_rx_pld_pcs_interface_hd_pcs10g_fifo_mode_rx reg_rx hssi_rx_pld_pcs_interface_hd_pcs8g_fifo_mode_rx hssi_rx_pld_pcs_interface_hd_pcs8g_fifo_mode_rx reg_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_fref_clk_hz hssi_rx_pld_pcs_interface_hd_pcs_channel_fref_clk_hz 322265625 hssi_rx_pld_pcs_interface_hd_pcs_channel_frequency_rules_en hssi_rx_pld_pcs_interface_hd_pcs_channel_frequency_rules_en enable hssi_rx_pld_pcs_interface_hd_pcs_channel_func_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_func_mode enable hssi_rx_pld_pcs_interface_hd_pcs_channel_hclk_clk_hz hssi_rx_pld_pcs_interface_hd_pcs_channel_hclk_clk_hz 0 hssi_rx_pld_pcs_interface_hd_pcs_channel_hip_en hssi_rx_pld_pcs_interface_hd_pcs_channel_hip_en disable hssi_rx_pld_pcs_interface_hd_pcs8g_hip_mode hssi_rx_pld_pcs_interface_hd_pcs8g_hip_mode disable hssi_rx_pld_pcs_interface_hd_pcs_channel_hrdrstctl_en hssi_rx_pld_pcs_interface_hd_pcs_channel_hrdrstctl_en disable hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_if_hrdrstctl_en hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_if_hrdrstctl_en disable hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx disable hssi_rx_pld_pcs_interface_hd_pcs10g_low_latency_en_rx hssi_rx_pld_pcs_interface_hd_pcs10g_low_latency_en_rx disable hssi_rx_pld_pcs_interface_hd_pcs_channel_low_latency_en_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_low_latency_en_rx disable hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en disable hssi_rx_pld_pcs_interface_hd_pcs10g_lpbk_en hssi_rx_pld_pcs_interface_hd_pcs10g_lpbk_en disable hssi_rx_pld_pcs_interface_hd_pcs8g_lpbk_en hssi_rx_pld_pcs_interface_hd_pcs8g_lpbk_en disable hssi_rx_pld_pcs_interface_hd_pcs_channel_lpbk_en hssi_rx_pld_pcs_interface_hd_pcs_channel_lpbk_en disable hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_lpbk_en hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_lpbk_en disable hssi_rx_pld_pcs_interface_hd_pcs_channel_operating_voltage hssi_rx_pld_pcs_interface_hd_pcs_channel_operating_voltage standard hssi_rx_pld_pcs_interface_hd_pcs_channel_pcs_ac_pwr_rules_en hssi_rx_pld_pcs_interface_hd_pcs_channel_pcs_ac_pwr_rules_en disable hssi_rx_pld_pcs_interface_hd_pcs_channel_pcs_pair_ac_pwr_uw_per_mhz hssi_rx_pld_pcs_interface_hd_pcs_channel_pcs_pair_ac_pwr_uw_per_mhz 0 hssi_rx_pld_pcs_interface_hd_pcs_channel_pcs_rx_ac_pwr_uw_per_mhz hssi_rx_pld_pcs_interface_hd_pcs_channel_pcs_rx_ac_pwr_uw_per_mhz 0 hssi_rx_pld_pcs_interface_pcs_rx_block_sel hssi_rx_pld_pcs_interface_pcs_rx_block_sel teng hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel teng_clk_out hssi_rx_pld_pcs_interface_pcs_rx_clk_sel hssi_rx_pld_pcs_interface_pcs_rx_clk_sel pcs_rx_clk hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en hip_rx_disable hssi_rx_pld_pcs_interface_pcs_rx_output_sel hssi_rx_pld_pcs_interface_pcs_rx_output_sel teng_output hssi_rx_pld_pcs_interface_hd_pcs_channel_pcs_rx_pwr_scaling_clk hssi_rx_pld_pcs_interface_hd_pcs_channel_pcs_rx_pwr_scaling_clk pma_rx_clk hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_8g_refclk_dig_nonatpg_mode_clk_hz hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_8g_refclk_dig_nonatpg_mode_clk_hz 0 hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_fifo_mode_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_fifo_mode_rx reg_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_pcs_refclk_dig_nonatpg_mode_clk_hz hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_pcs_refclk_dig_nonatpg_mode_clk_hz 0 hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_rx_clk_hz hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_rx_clk_hz 0 hssi_rx_pld_pcs_interface_hd_pcs10g_pma_dw_rx hssi_rx_pld_pcs_interface_hd_pcs10g_pma_dw_rx pma_64b_rx hssi_rx_pld_pcs_interface_hd_pcs8g_pma_dw_rx hssi_rx_pld_pcs_interface_hd_pcs8g_pma_dw_rx pma_10b_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_dw_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_dw_rx pma_64b_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_pma_dw_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_pma_dw_rx pma_64b_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_rx_clk_hz hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_rx_clk_hz 161132812 hssi_rx_pld_pcs_interface_hd_g3pcs_prot_mode hssi_rx_pld_pcs_interface_hd_g3pcs_prot_mode disabled_prot_mode hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx disabled_prot_mode_rx hssi_rx_pld_pcs_interface_hd_pcs10g_prot_mode_rx hssi_rx_pld_pcs_interface_hd_pcs10g_prot_mode_rx basic_mode_rx hssi_rx_pld_pcs_interface_hd_pcs8g_prot_mode_rx hssi_rx_pld_pcs_interface_hd_pcs8g_prot_mode_rx disabled_prot_mode_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_prot_mode_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_prot_mode_rx basic_10gpcs_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_if_prot_mode_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_if_prot_mode_rx teng_reg_mode_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_prot_mode_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_prot_mode_rx teng_basic_mode_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_prot_mode_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_prot_mode_rx teng_mode_rx hssi_rx_pld_pcs_interface_hd_pcs10g_shared_fifo_width_rx hssi_rx_pld_pcs_interface_hd_pcs10g_shared_fifo_width_rx single_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_shared_fifo_width_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_shared_fifo_width_rx single_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_shared_fifo_width_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_shared_fifo_width_rx single_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_sim_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_sim_mode disable hssi_rx_pld_pcs_interface_hd_pcs_channel_speed_grade hssi_rx_pld_pcs_interface_hd_pcs_channel_speed_grade e2 hssi_rx_pld_pcs_interface_hd_g3pcs_sup_mode hssi_rx_pld_pcs_interface_hd_g3pcs_sup_mode user_mode hssi_rx_pld_pcs_interface_hd_krfec_sup_mode hssi_rx_pld_pcs_interface_hd_krfec_sup_mode user_mode hssi_rx_pld_pcs_interface_hd_pcs10g_sup_mode hssi_rx_pld_pcs_interface_hd_pcs10g_sup_mode user_mode hssi_rx_pld_pcs_interface_hd_pcs8g_sup_mode hssi_rx_pld_pcs_interface_hd_pcs8g_sup_mode user_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_sup_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_sup_mode user_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_if_sup_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_pld_if_sup_mode user_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_sup_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_pma_if_sup_mode user_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_sup_mode hssi_rx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_sup_mode user_mode hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode tx hssi_rx_pld_pcs_interface_hd_pcs10g_test_bus_mode hssi_rx_pld_pcs_interface_hd_pcs10g_test_bus_mode rx hssi_rx_pld_pcs_interface_hd_pcs_channel_transparent_pcs_rx hssi_rx_pld_pcs_interface_hd_pcs_channel_transparent_pcs_rx disable hssi_rx_pld_pcs_interface_silicon_rev hssi_rx_pld_pcs_interface_silicon_rev 14nm5bcr2eb hssi_rx_pld_pcs_interface_reconfig_settings hssi_rx_pld_pcs_interface_reconfig_settings {} hssi_tx_pcs_pma_interface_bypass_pma_txelecidle hssi_tx_pcs_pma_interface_bypass_pma_txelecidle true hssi_tx_pcs_pma_interface_channel_operation_mode hssi_tx_pcs_pma_interface_channel_operation_mode tx_rx_pair_enabled hssi_tx_pcs_pma_interface_lpbk_en hssi_tx_pcs_pma_interface_lpbk_en disable hssi_tx_pcs_pma_interface_master_clk_sel hssi_tx_pcs_pma_interface_master_clk_sel master_tx_pma_clk hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx other_prot_mode hssi_tx_pcs_pma_interface_pldif_datawidth_mode hssi_tx_pcs_pma_interface_pldif_datawidth_mode pldif_data_10bit hssi_tx_pcs_pma_interface_pma_dw_tx hssi_tx_pcs_pma_interface_pma_dw_tx pma_64b_tx hssi_tx_pcs_pma_interface_pma_if_dft_en hssi_tx_pcs_pma_interface_pma_if_dft_en dft_dis hssi_tx_pcs_pma_interface_pmagate_en hssi_tx_pcs_pma_interface_pmagate_en pmagate_dis hssi_tx_pcs_pma_interface_prbs9_dwidth hssi_tx_pcs_pma_interface_prbs9_dwidth prbs9_64b hssi_tx_pcs_pma_interface_prbs_clken hssi_tx_pcs_pma_interface_prbs_clken prbs_clk_dis hssi_tx_pcs_pma_interface_prbs_gen_pat hssi_tx_pcs_pma_interface_prbs_gen_pat prbs_gen_dis hssi_tx_pcs_pma_interface_prot_mode_tx hssi_tx_pcs_pma_interface_prot_mode_tx teng_basic_mode_tx hssi_tx_pcs_pma_interface_sq_wave_num hssi_tx_pcs_pma_interface_sq_wave_num sq_wave_default hssi_tx_pcs_pma_interface_sqwgen_clken hssi_tx_pcs_pma_interface_sqwgen_clken sqwgen_clk_dis hssi_tx_pcs_pma_interface_sup_mode hssi_tx_pcs_pma_interface_sup_mode user_mode hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion tx_dyn_polinv_dis hssi_tx_pcs_pma_interface_tx_pma_data_sel hssi_tx_pcs_pma_interface_tx_pma_data_sel ten_g_pcs hssi_tx_pcs_pma_interface_tx_static_polarity_inversion hssi_tx_pcs_pma_interface_tx_static_polarity_inversion tx_stat_polinv_dis hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock uhsif_filt_stepsz_b4lock_2 hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value 0 hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock uhsif_filt_cntthr_b4lock_8 hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period uhsif_dcn_test_period_4 hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable uhsif_dcn_test_mode_disable hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh uhsif_dzt_cnt_thr_2 hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable uhsif_dzt_disable hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window uhsif_dzt_obr_win_16 hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size uhsif_dzt_skipsz_4 hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel uhsif_index_cram hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin uhsif_dcn_margin_2 hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value 0 hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control uhsif_dft_dz_det_val_0 hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control uhsif_dft_up_val_0 hssi_tx_pcs_pma_interface_uhsif_enable hssi_tx_pcs_pma_interface_uhsif_enable uhsif_disable hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock uhsif_lkd_segsz_aflock_512 hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock uhsif_lkd_segsz_b4lock_16 hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value 0 hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value 0 hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value 0 hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value 0 hssi_tx_pcs_pma_interface_silicon_rev hssi_tx_pcs_pma_interface_silicon_rev 14nm5bcr2eb hssi_tx_pcs_pma_interface_reconfig_settings hssi_tx_pcs_pma_interface_reconfig_settings {} hssi_tx_pld_pcs_interface_hd_pcs10g_advanced_user_mode_tx hssi_tx_pld_pcs_interface_hd_pcs10g_advanced_user_mode_tx disable hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode tx_rx_pair_enabled hssi_tx_pld_pcs_interface_hd_pcs10g_channel_operation_mode hssi_tx_pld_pcs_interface_hd_pcs10g_channel_operation_mode tx_rx_pair_enabled hssi_tx_pld_pcs_interface_hd_pcs8g_channel_operation_mode hssi_tx_pld_pcs_interface_hd_pcs8g_channel_operation_mode tx_rx_pair_enabled hssi_tx_pld_pcs_interface_hd_pcs_channel_channel_operation_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_channel_operation_mode tx_rx_pair_enabled hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_channel_operation_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_channel_operation_mode tx_rx_pair_enabled hssi_tx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_channel_operation_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_channel_operation_mode tx_rx_pair_enabled hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_ctrl_plane_bonding hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_ctrl_plane_bonding individual hssi_tx_pld_pcs_interface_hd_pcs10g_ctrl_plane_bonding_tx hssi_tx_pld_pcs_interface_hd_pcs10g_ctrl_plane_bonding_tx individual_tx hssi_tx_pld_pcs_interface_hd_pcs8g_ctrl_plane_bonding_tx hssi_tx_pld_pcs_interface_hd_pcs8g_ctrl_plane_bonding_tx individual_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_ctrl_plane_bonding_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_ctrl_plane_bonding_tx individual_tx hssi_tx_pld_pcs_interface_hd_pcs10g_fifo_mode_tx hssi_tx_pld_pcs_interface_hd_pcs10g_fifo_mode_tx reg_tx hssi_tx_pld_pcs_interface_hd_pcs8g_fifo_mode_tx hssi_tx_pld_pcs_interface_hd_pcs8g_fifo_mode_tx reg_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_frequency_rules_en hssi_tx_pld_pcs_interface_hd_pcs_channel_frequency_rules_en enable hssi_tx_pld_pcs_interface_hd_pcs_channel_func_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_func_mode enable hssi_tx_pld_pcs_interface_hd_pcs_channel_hclk_clk_hz hssi_tx_pld_pcs_interface_hd_pcs_channel_hclk_clk_hz 0 hssi_tx_pld_pcs_interface_hd_pcs_channel_hip_en hssi_tx_pld_pcs_interface_hd_pcs_channel_hip_en disable hssi_tx_pld_pcs_interface_hd_pcs8g_hip_mode hssi_tx_pld_pcs_interface_hd_pcs8g_hip_mode disable hssi_tx_pld_pcs_interface_hd_pcs_channel_hrdrstctl_en hssi_tx_pld_pcs_interface_hd_pcs_channel_hrdrstctl_en disable hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_if_hrdrstctl_en hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_if_hrdrstctl_en disable hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx disable hssi_tx_pld_pcs_interface_hd_pcs10g_low_latency_en_tx hssi_tx_pld_pcs_interface_hd_pcs10g_low_latency_en_tx disable hssi_tx_pld_pcs_interface_hd_pcs_channel_low_latency_en_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_low_latency_en_tx disable hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en disable hssi_tx_pld_pcs_interface_hd_pcs10g_lpbk_en hssi_tx_pld_pcs_interface_hd_pcs10g_lpbk_en disable hssi_tx_pld_pcs_interface_hd_pcs8g_lpbk_en hssi_tx_pld_pcs_interface_hd_pcs8g_lpbk_en disable hssi_tx_pld_pcs_interface_hd_pcs_channel_lpbk_en hssi_tx_pld_pcs_interface_hd_pcs_channel_lpbk_en disable hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_lpbk_en hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_lpbk_en disable hssi_tx_pld_pcs_interface_hd_pcs_channel_pcs_tx_ac_pwr_uw_per_mhz hssi_tx_pld_pcs_interface_hd_pcs_channel_pcs_tx_ac_pwr_uw_per_mhz 0 hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel teng_clk_out hssi_tx_pld_pcs_interface_pcs_tx_clk_source hssi_tx_pld_pcs_interface_pcs_tx_clk_source teng hssi_tx_pld_pcs_interface_pcs_tx_data_source hssi_tx_pld_pcs_interface_pcs_tx_data_source hip_disable hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en delay1_clk_disable hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel pcs_tx_clk hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl delay1_path0 hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel one_ff_delay hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en delay2_clk_disable hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl delay2_path0 hssi_tx_pld_pcs_interface_pcs_tx_output_sel hssi_tx_pld_pcs_interface_pcs_tx_output_sel teng_output hssi_tx_pld_pcs_interface_hd_pcs_channel_pcs_tx_pwr_scaling_clk hssi_tx_pld_pcs_interface_hd_pcs_channel_pcs_tx_pwr_scaling_clk pma_tx_clk hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_8g_refclk_dig_nonatpg_mode_clk_hz hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_8g_refclk_dig_nonatpg_mode_clk_hz 0 hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_fifo_mode_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_fifo_mode_tx reg_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_pcs_refclk_dig_nonatpg_mode_clk_hz hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_pcs_refclk_dig_nonatpg_mode_clk_hz 0 hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_tx_clk_hz hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_tx_clk_hz 0 hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_uhsif_tx_clk_hz hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_uhsif_tx_clk_hz 0 hssi_tx_pld_pcs_interface_hd_pcs10g_pma_dw_tx hssi_tx_pld_pcs_interface_hd_pcs10g_pma_dw_tx pma_64b_tx hssi_tx_pld_pcs_interface_hd_pcs8g_pma_dw_tx hssi_tx_pld_pcs_interface_hd_pcs8g_pma_dw_tx pma_10b_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_dw_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_dw_tx pma_64b_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_pma_dw_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_pma_dw_tx pma_64b_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_tx_clk_hz hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_tx_clk_hz 161132812 hssi_tx_pld_pcs_interface_hd_g3pcs_prot_mode hssi_tx_pld_pcs_interface_hd_g3pcs_prot_mode disabled_prot_mode hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx disabled_prot_mode_tx hssi_tx_pld_pcs_interface_hd_pcs10g_prot_mode_tx hssi_tx_pld_pcs_interface_hd_pcs10g_prot_mode_tx basic_mode_tx hssi_tx_pld_pcs_interface_hd_pcs8g_prot_mode_tx hssi_tx_pld_pcs_interface_hd_pcs8g_prot_mode_tx disabled_prot_mode_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_prot_mode_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_prot_mode_tx basic_10gpcs_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_if_prot_mode_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_if_prot_mode_tx teng_reg_mode_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_prot_mode_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_prot_mode_tx teng_basic_mode_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_prot_mode_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_prot_mode_tx teng_mode_tx hssi_tx_pld_pcs_interface_hd_pcs10g_shared_fifo_width_tx hssi_tx_pld_pcs_interface_hd_pcs10g_shared_fifo_width_tx single_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_shared_fifo_width_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_shared_fifo_width_tx single_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_shared_fifo_width_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_shared_fifo_width_tx single_tx hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_sim_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_sim_mode disable hssi_tx_pld_pcs_interface_hd_pcs_channel_speed_grade hssi_tx_pld_pcs_interface_hd_pcs_channel_speed_grade e2 hssi_tx_pld_pcs_interface_hd_g3pcs_sup_mode hssi_tx_pld_pcs_interface_hd_g3pcs_sup_mode user_mode hssi_tx_pld_pcs_interface_hd_krfec_sup_mode hssi_tx_pld_pcs_interface_hd_krfec_sup_mode user_mode hssi_tx_pld_pcs_interface_hd_pcs10g_sup_mode hssi_tx_pld_pcs_interface_hd_pcs10g_sup_mode user_mode hssi_tx_pld_pcs_interface_hd_pcs8g_sup_mode hssi_tx_pld_pcs_interface_hd_pcs8g_sup_mode user_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_sup_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_sup_mode user_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_if_sup_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_pld_if_sup_mode user_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_sup_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_pma_if_sup_mode user_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_sup_mode hssi_tx_pld_pcs_interface_hd_pcs_channel_share_fifo_mem_sup_mode user_mode hssi_tx_pld_pcs_interface_silicon_rev hssi_tx_pld_pcs_interface_silicon_rev 14nm5bcr2eb hssi_tx_pld_pcs_interface_reconfig_settings hssi_tx_pld_pcs_interface_reconfig_settings {} device Device 1SX280HN2F43E2VG deviceFamily Device family Stratix 10 deviceSpeedGrade Device Speed Grade 2 generationId Generation Id 0 bonusData bonusData bonusData { element xcvr_native_s10_htile_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> false false