set_global_assignment -name TOP_LEVEL_ENTITY ip_management
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:32:45  3月 23, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Pro Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name DEVICE 1SX280HN2F43E2VG
set_global_assignment -name FAMILY "Stratix 10"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1760
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 2
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name IP_FILE atx_5g.ip
set_global_assignment -name IP_FILE atx_5g_4cb.ip
set_global_assignment -name IP_FILE atx_12g.ip
set_global_assignment -name IP_FILE phy_rst_ctrl_4ch.ip
set_global_assignment -name IP_FILE phy_25g.ip
set_global_assignment -name IP_FILE phy_10g_4ch.ip
set_global_assignment -name IP_FILE phy_10g_4cb.ip