Intel Corporation rst_rel s10_user_rst_clkgate_0 19.3.2 ninit_done ninit_done ninit_done associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH altera_s10_user_rst_clkgate QUARTUS_SYNTH ninit_done out STD_LOGIC QUARTUS_SYNTH Intel Corporation rst_rel altera_s10_user_rst_clkgate 19.3.2 outputType Type of reset output port Conduit Interface DEVICE_FAMILY Device family Agilex device Device AGFB014R24B2E2V deviceFamily Device family Agilex deviceSpeedGrade Device Speed Grade 2 generationId Generation Id 0 bonusData bonusData bonusData { element s10_user_rst_clkgate_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> false false