Intel Corporation phy_10g_8ch xcvrnphy_fme_0 4.1.0 tx_dll_lock tx_dll_lock tx_dll_lock associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output reset reset reset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_ready tx_ready tx_ready associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_ready rx_ready rx_ready associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_pma_ready tx_pma_ready tx_pma_ready associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_pma_ready rx_pma_ready rx_pma_ready associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_serial_data tx_serial_data tx_serial_data associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_serial_data_n tx_serial_data_n tx_serial_data_n associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_serial_data rx_serial_data rx_serial_data associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_serial_data_n rx_serial_data_n rx_serial_data_n associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input pll_refclk0 clk pll_refclk0 associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_is_lockedtodata rx_is_lockedtodata rx_is_lockedtodata associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_pmaif_fifo_underflow rx_pmaif_fifo_underflow rx_pmaif_fifo_underflow associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_pmaif_bitslip rx_pmaif_bitslip rx_pmaif_bitslip associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_parallel_data tx_parallel_data tx_parallel_data associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_parallel_data rx_parallel_data rx_parallel_data associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_coreclkin clk tx_coreclkin associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_coreclkin clk rx_coreclkin associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_clkout clk tx_clkout associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_clkout2 clk tx_clkout2 associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_clkout clk rx_clkout associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_clkout2 clk rx_clkout2 associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_fifo_full tx_fifo_full tx_fifo_full associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_fifo_empty tx_fifo_empty tx_fifo_empty associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_fifo_pfull tx_fifo_pfull tx_fifo_pfull associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_fifo_pempty tx_fifo_pempty tx_fifo_pempty associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_fifo_full rx_fifo_full rx_fifo_full associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_fifo_empty rx_fifo_empty rx_fifo_empty associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_fifo_pfull rx_fifo_pfull rx_fifo_pfull associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_fifo_pempty rx_fifo_pempty rx_fifo_pempty associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_fifo_rd_en rx_fifo_rd_en rx_fifo_rd_en associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_enh_pmaif_fifo_almost_full tx_enh_pmaif_fifo_almost_full tx_enh_pmaif_fifo_almost_full associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_enh_pmaif_fifo_almost_empty tx_enh_pmaif_fifo_almost_empty tx_enh_pmaif_fifo_almost_empty associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_enh_pmaif_fifo_overflow tx_enh_pmaif_fifo_overflow tx_enh_pmaif_fifo_overflow associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_enh_pmaif_fifo_underflow tx_enh_pmaif_fifo_underflow tx_enh_pmaif_fifo_underflow associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_enh_pmaif_fifo_overflow rx_enh_pmaif_fifo_overflow rx_enh_pmaif_fifo_overflow associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH xcvrnphy_fme QUARTUS_SYNTH tx_dll_lock out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH reset in 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_ready out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_ready out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_pma_ready out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_pma_ready out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_serial_data out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_serial_data_n out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_serial_data in 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_serial_data_n in 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH pll_refclk0 in STD_LOGIC QUARTUS_SYNTH rx_is_lockedtodata out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_pmaif_fifo_underflow out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_pmaif_bitslip in 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_parallel_data in 0 639 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_parallel_data out 0 639 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_coreclkin in 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_coreclkin in 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_clkout out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_clkout2 out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_clkout out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_clkout2 out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_fifo_full out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_fifo_empty out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_fifo_pfull out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_fifo_pempty out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_fifo_full out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_fifo_empty out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_fifo_pfull out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_fifo_pempty out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_fifo_rd_en in 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_enh_pmaif_fifo_almost_full out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_enh_pmaif_fifo_almost_empty out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_enh_pmaif_fifo_overflow out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_enh_pmaif_fifo_underflow out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_enh_pmaif_fifo_overflow out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH Intel Corporation phy_10g_8ch xcvrnphy_fme 4.1.0 dr_25g_cpri_nphy dr_25g_cpri_nphy 0 device_family device_family Agilex device device AGFB014R24B2E2V device_die_types device_die_types HSSI_WHR,HSSI_CRETE3,MAIN_FM6 device_die_revisions device_die_revisions HSSI_WHR_REVA,HSSI_CRETE3_REVA,MAIN_FM6_REVB design_environment design_environment NATIVE message_level Message level for rule violations error enable_infuture_options Enable in-future options 0 enable_ehip_options Enable EHIP options 0 enable_interlaken_options Enable Interlaken options 0 enable_rsfec_fc_cpri_options_checkbox Enable Fibre-Channel/CPRI Mode options 0 enable_advanced_options Enable advanced options 0 enable_inprogress_options Enable in-progress options: this will be hidden in future 1 enable_debug_options Enable debug options 0 support_mode Protocol support mode user_mode support_mode_hssi_adpt HSSI adapter support mode user_mode support_mode_pld_adpt PLD adapter support mode user_mode protocol_mode Transceiver configuration rules pma_direct_gb_64_66 duplex_mode Transceiver mode duplex channels Number of data channels 8 ptp_data_channels Number of PTP data channels 4 ptp_ethernet_data_rsfec_enabled Is RSFEC enabled for ethernet data 0 deskew_pma_only_enable Enable de-skew 0 rsfec_enable Enable RSFEC 0 enable_split_interface Provide separate interface for each channel 0 rcfg_iface_enable Enable datapath and interface reconfiguration 0 user_preserve_unused_xcvr_channels Preserve Unused Transceiver Channels 0 user_bti_channel_clock_select Reference clock selection for preserved channels 0 user_bti_channel_ref_clock_freq_mhz Reference clock frequency for preserved channels 100 enable_simple_interface Enable simplified data interface 0 enable_direct_reset_control Enable direct reset control 0 parallel_lpbk_mode Parallel loopback mode disabled loopback_tx_clk_sel Parallel loopback mode TX clock source selection internal_clk enable_manual_reset Enable manual reset 0 reset_separation_ns Minimum seperation time between reset assertion and deassertion 200 space_ns Minimum spacing time between AIB, XCVRIF, RSFEC resets 100 reduced_sim_time Enable fast simulation for controller 1 reduced_reset_sim_time Enable fast simulation for sequencer 1 enable_ind_txrx Enable individual TX and RX reset 0 enable_ind_channel Use separate TX/RX reset per channel 0 enable_seq Enable TX/RX reset sequencing 0 t_tx_reset TX reset duration 100 t_rx_reset RX reset duration 100 enable_pma_reset Enable pma reset ports and feature 0 enable_spico_reset Enable spico reset ports and feature 0 enable_port_latency_measurement Enable latency measurement ports 0 enable_latency_measurement_feature Enable latency measurement feature 0 enable_ptp_measurement_port Enable PTP measurement ports 0 enable_ptp_measurement_feature Enable PTP measurement feature 0 rx_bit_counter_rollover Bit counter rollover 0 pll_refclk_cnt Number of reference clock inputs 1 pll_select Initial PLL reference clock input selection 0 pll_outclk_freq_mhz PLL output clock frequency 400 pll_refclk_freq_mhz PLL reference clock frequency 250.000000 pma_example_qsf_strings Display sample QSF assignments 0 pma_disable Disable PMA 0 enable_port_pll_refclk Enable pll_refclk port 0 pma_plls Number of reference clock inputs 1 pma_tx_pll_select Initial primary transceiver reference clock input selection 0 pma_rx_dedicated_refclk_enable Enable dedicated RX reference clock input 0 pma_rx_dedicated_refclk_select Dedicated RX reference clock input selection 0 pma_an_constraints_enable Enable Auto Negotiation Constraints 0 pma_seq_enable Enable PMA Sequencer 1 user_set_int_seq_serd_en SerDes/Output Driver Enable Mode seq_en_all user_set_serdes_en_seq SerDes POR Exit Configuration en_serdes_seq pma_ical_enable Enable iCal IP 0 pma_ical_poweron_enable Enable iCal in poweron sequence 1 pma_tx_modulation TX PMA modulation type NRZ pma_tx_data_rate TX PMA data rate 10312.5 pma_tx_clkdiv66_enable Enable TX PMA div66 clock 1 pma_tx_bonding_enable Enable TX PMA bonding 0 pma_tx_pll_post_divider TX PMA clockout post divider 1 pma_tx_pll_refclk_freq_mhz TX PMA reference clock frequency 156.250000 pma_tx_eq_pre_tap pma_tx_eq_pre_tap 0 pma_tx_eq_main_tap pma_tx_eq_main_tap 0 pma_tx_eq_post_tap pma_tx_eq_post_tap 0 pma_tx_eq_vod pma_tx_eq_vod 0 pma_tx_eq_slew_rate pma_tx_eq_slew_rate 0 pma_tx_eq_powerup_disable Use default TX PMA pre-equalization settings 1 pma_tx_eq_atten_tap Attenuation 0 pma_tx_eq_pre1_tap Pre-tap 1 0 pma_tx_eq_pre2_tap Pre-tap 2 0 pma_tx_eq_pre3_tap Pre-tap 3 0 pma_tx_eq_post1_tap Post-tap 1 0 pma_rx_modulation RX PMA modulation type NRZ pma_rx_data_rate RX PMA data rate 10312.5 pma_rx_clkdiv66_enable Enable RX PMA div66 clock 1 pma_rx_clkhalfrate_enable Enable RX PMA half-rate clock 0 pma_rx_clkfullrate_enable Enable RX PMA full-rate clock 1 pma_rx_pll_post_divider RX PMA clkout post divider 1 pma_rx_pll_refclk_freq_mhz RX PMA reference clock frequency 156.250000 enable_port_rx_pma_en Enable rx_pma_en port 0 enable_port_rx_pma_clkslip Enable rx_pma_clkslip port 0 enable_port_rx_is_lockedtodata Enable rx_is_lockedtodata port 1 enable_port_rx_pma_elecidle Enable rx_pma_elecidle port 0 enable_port_tx_pma_en Enable tx_pma_en port 0 pldif_manual_transfer_clk_mode_enable Enable manual transfer clock setting mode 0 pldif_tx_manual_mode_transfer_clk_hz Manual mode TX transfer clock 0 pldif_rx_manual_mode_transfer_clk_hz Manual mode RX transfer clock 0 pldif_tx_fast_pipeln_reg_enable Enable TX fast pipeline registers 0 pldif_rx_fast_pipeln_reg_enable Enable RX fast pipeline registers 0 set_op_mode_enable Enable setting adapter operation mode 0 tx_nd_maib_op_mode tx_nd_maib_op_mode tx_dcc_enable rx_nd_maib_op_mode rx_nd_maib_op_mode rx_dll_enable cr3_advanced_aib_settings_enable Enable advanced transceiver adapter settings 0 l_hssi_adapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass HSSI FIFO status signals bypass disable l_hssi_adapt_rx_rx_pld_8g_wa_boundary_polling_bypass Boundary polling bypass disable l_hssi_adapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass PCIE sw done polling bypass disable l_hssi_adapt_rx_rx_pld_pma_reser_in_polling_bypass Reser in polling bypass disable l_hssi_adapt_rx_rx_pld_pma_testbus_polling_bypass Testbus polling bypass disable l_hssi_adapt_rx_rx_pld_test_data_polling_bypass Test data polling bypass disable l_hssi_adapt_tx_dv_gating TX dv gating disable pldif_debug_ports_enable Enable PCS reset status ports 0 pldif_tx_fifo_mode TX Core interface FIFO mode phase_comp pldif_tx_fifo_pfull_thld TX Core interface FIFO partially full threshold 10 pldif_tx_fifo_pempty_thld TX Core interface FIFO partially empty threshold 2 pldif_tx_double_width_transfer_enable Enable TX double width transfer 0 enable_port_tx_fifo_full Enable tx_fifo_full port 1 enable_port_tx_fifo_empty Enable tx_fifo_empty port 1 enable_port_tx_fifo_pfull Enable tx_fifo_pfull port 1 enable_port_tx_fifo_pempty Enable tx_fifo_pempty port 1 enable_port_tx_pcs_fifo_full Enable tx_pcs_fifo_full port 0 enable_port_tx_pcs_fifo_empty Enable tx_pcs_fifo_empty port 0 enable_port_tx_dll_lock Enable tx_dll_lock port 1 pldif_rx_fifo_mode RX Core interface FIFO mode phase_comp pldif_rx_fifo_pfull_thld RX Core interface FIFO partially full threshold 10 pldif_rx_fifo_pempty_thld RX Core interface FIFO partially empty threshold 2 pldif_rx_double_width_transfer_enable Enable RX double width transfer 0 enable_port_rx_fifo_full Enable rx_fifo_full port 1 enable_port_rx_fifo_empty Enable rx_fifo_empty port 1 enable_port_rx_fifo_pfull Enable rx_fifo_pfull port 1 enable_port_rx_fifo_pempty Enable rx_fifo_pempty port 1 enable_port_rx_fifo_rd_en Enable rx_fifo_rd_en port 1 enable_port_rx_pcs_fifo_full Enable rx_pcs_fifo_full port 0 enable_port_rx_pcs_fifo_empty Enable rx_pcs_fifo_empty port 0 pldif_tx_clkout_sel Selected tx_clkout clock source div66 enable_port_tx_clkout2 Enable tx_clkout2 port 1 pldif_tx_clkout2_sel Selected tx_clkout2 clock source half-rate enable_port_tx_clkout_hioint Enable tx_clkout_hioint port 0 enable_port_tx_clkout2_hioint Enable tx_clkout2_hioint port 0 pldif_tx_coreclkin_clock_network Selected tx_coreclkin clock network dedicated pldif_tx_coreclkin2_external_clk_enable Enable external clock mode 0 enable_port_tx_clkin2 Enable tx_coreclkin2 port 0 pldif_tx_coreclkin2_clock_network Selected tx_coreclkin2 clock network dedicated pldif_rx_clkout_sel Selected rx_clkout clock source div66 enable_port_rx_clkout2 Enable rx_clkout2 port 1 pldif_rx_clkout2_sel Selected rx_clkout2 clock source half-rate enable_port_rx_clkout_hioint Enable rx_clkout_hioint port 0 enable_port_rx_clkout2_hioint Enable rx_clkout2_hioint port 0 pldif_rx_coreclkin_clock_network Selected rx_coreclkin clock network dedicated pcs_manual_rx_fifo_rd_clk_sel_enable Enable manual RX PCS FIFO read clk selection 0 pcs_rx_fifo_rd_clk_sel RX PCS FIFO read clk tx_pma_clk pldif_osc_clk_divider OSC clock division factor 1 pmaif_tx_to_rx_parallel_loopback_enable Enable TX to RX parallel loopback 0 enable_port_pma_initialized Enable pma_initialized port 0 pmaif_tx_soft_reset_enable Enable TX PMA interface soft reset 0 pmaif_tx_width TX PMA interface width 32 pmaif_tx_bit_interleaving_enable Enable TX PMA bit interleaving 0 pmaif_rx_soft_reset_enable Enable RX PMA interface soft reset 0 pmaif_rx_width RX PMA interface width 32 pmaif_rx_bit_interleaving_enable Enable RX PMA bit interleaving 0 pmaif_tx_fifo_mode TX PMA interface FIFO mode. elastic pmaif_tx_fifo_wr_full_enable Enable TX PMA interface FIFO write when full 0 pmaif_tx_fifo_rd_empty_enable Enable TX PMA interface FIFO read when empty 0 pmaif_tx_fifo_afull_thld TX PMA interface FIFO almost full threshold 20 pmaif_tx_fifo_full_thld TX PMA interface FIFO full threshold 31 pmaif_tx_fifo_aempty_thld TX PMA interface FIFO almost empty threshold 7 pmaif_tx_fifo_empty_thld TX PMA interface FIFO empty threshold 0 enable_port_tx_enh_pmaif_fifo_almost_full Enable tx_enh_pmaif_fifo_almost_full port 1 enable_port_tx_enh_pmaif_fifo_almost_empty Enable tx_enh_pmaif_fifo_almost_empty port 1 enable_port_tx_enh_pmaif_fifo_overflow Enable tx_enh_pmaif_fifo_overflow port 1 enable_port_tx_enh_pmaif_fifo_underflow Enable tx_enh_pmaif_fifo_underflow port 1 pmaif_rx_fifo_wr_full_enable Enable RX PMA interface FIFO write when full 0 pmaif_rx_fifo_rd_empty_enable Enable RX PMA interface FIFO read when empty 0 pmaif_rx_fifo_afull_thld RX PMA interface FIFO almost full threshold 20 pmaif_rx_fifo_full_thld RX PMA interface FIFO full threshold 31 pmaif_rx_fifo_aempty_thld RX PMA interface FIFO almost empty threshold 7 pmaif_rx_fifo_empty_thld RX PMA interface FIFO empty threshold 0 enable_port_rx_pmaif_fifo_underflow Enable rx_pmaif_fifo_underflow port 1 enable_port_rx_enh_pmaif_fifo_overflow Enable rx_enh_pmaif_fifo_overflow port 1 pmaif_rx_fifo_wr_clk_enable Enable RX PMA interface FIFO write clock and gearbox clock 1 pmaif_tx_gb_mode TX PMA interface gearbox mode tx_gb_64_64 pmaif_rx_gb_mode RX PMA interface gearbox mode rx_gb_64_64 pmaif_tx_gb_bit_reversal_enable Enable TX bit reversal 1 pmaif_rx_gb_bit_reversal_enable Enable RX bit reversal 1 pmaif_tx_gb_sh_bit_reversal_enable Enable TX sync header bit reversal 1 pmaif_rx_gb_sh_bit_reversal_enable Enable RX sync header bit reversal 1 pmaif_tx_gb_word_order TX gearbox word order lower pmaif_rx_gb_word_order RX gearbox word order lower pmaif_tx_gb_bitslip_enable Enable TX data bitslip 0 enable_port_tx_pmaif_bitslip Enable tx_pmaif_bitslip port 0 pmaif_rx_gb_bitslip_enable Enable RX data bitslip 1 enable_port_rx_pmaif_bitslip Enable rx_pmaif_bitslip port 1 pmaif_tx_gb_sh_bit_mode TX sync header location bit1-bit0 pmaif_rx_gb_sh_bit_mode RX sync header location bit65-bit64 pmaif_tx_gb_width_adapt_enable Enable TX PMA interface width-adapter 0 pmaif_rx_gb_width_adapt_enable Enable RX PMA interface width-adapter 0 elane_is_usr_avmm elane_is_usr_avmm false elane_ehip_dist_clk_sel elane_ehip_dist_clk_sel 0 elane_fec_dist_clk_sel elane_fec_dist_clk_sel 0 elane_sim_mode elane_sim_mode enable elane_ehip_rate elane_ehip_rate rate_100gx4 elane_func_mode elane_func_mode disable elane_powerdown_mode elane_powerdown_mode powerup elane_am_encoding40g_0 elane_am_encoding40g_0 9467463 elane_am_encoding40g_1 elane_am_encoding40g_1 15779046 elane_am_encoding40g_2 elane_am_encoding40g_2 12936603 elane_am_encoding40g_3 elane_am_encoding40g_3 10647869 elane_check_random_idles elane_check_random_idles disable elane_disable_link_fault_rf elane_disable_link_fault_rf disable elane_force_link_fault_rf elane_force_link_fault_rf disable elane_ehip_mode elane_ehip_mode ehip_disable elane_enable_rx_stats_snapshot elane_enable_rx_stats_snapshot disable elane_enable_tx_stats_snapshot elane_enable_tx_stats_snapshot disable elane_enforce_max_frame_size elane_enforce_max_frame_size disable elane_flow_control elane_flow_control none elane_tx_mac_data_flow elane_tx_mac_data_flow enable elane_source_address_insertion elane_source_address_insertion disable elane_strict_sfd_checking elane_strict_sfd_checking disable elane_txmac_saddr elane_txmac_saddr 73588229205 elane_rx_preamble_passthrough elane_rx_preamble_passthrough disable elane_tx_ipg_size elane_tx_ipg_size ipg_12 elane_tx_preamble_passthrough elane_tx_preamble_passthrough disable elane_tx_vlan_detection elane_tx_vlan_detection enable elane_tx_max_frame_size elane_tx_max_frame_size 1518 elane_ipg_removed_per_am_period elane_ipg_removed_per_am_period 20 elane_flow_control_holdoff_mode elane_flow_control_holdoff_mode per_queue elane_holdoff_quanta elane_holdoff_quanta 65535 elane_pause_quanta elane_pause_quanta 65535 elane_pfc_holdoff_quanta_0 elane_pfc_holdoff_quanta_0 65535 elane_pfc_holdoff_quanta_1 elane_pfc_holdoff_quanta_1 65535 elane_pfc_holdoff_quanta_2 elane_pfc_holdoff_quanta_2 65535 elane_pfc_holdoff_quanta_3 elane_pfc_holdoff_quanta_3 65535 elane_pfc_holdoff_quanta_4 elane_pfc_holdoff_quanta_4 65535 elane_pfc_holdoff_quanta_5 elane_pfc_holdoff_quanta_5 65535 elane_pfc_holdoff_quanta_6 elane_pfc_holdoff_quanta_6 65535 elane_pfc_holdoff_quanta_7 elane_pfc_holdoff_quanta_7 65535 elane_pfc_pause_quanta_0 elane_pfc_pause_quanta_0 65535 elane_pfc_pause_quanta_1 elane_pfc_pause_quanta_1 65535 elane_pfc_pause_quanta_2 elane_pfc_pause_quanta_2 65535 elane_pfc_pause_quanta_3 elane_pfc_pause_quanta_3 65535 elane_pfc_pause_quanta_4 elane_pfc_pause_quanta_4 65535 elane_pfc_pause_quanta_5 elane_pfc_pause_quanta_5 65535 elane_pfc_pause_quanta_6 elane_pfc_pause_quanta_6 65535 elane_pfc_pause_quanta_7 elane_pfc_pause_quanta_7 65535 elane_forward_rx_pause_requests elane_forward_rx_pause_requests disable elane_tx_pause_daddr elane_tx_pause_daddr 1652522221569 elane_tx_pause_saddr elane_tx_pause_saddr 247393538562781 elane_rx_pause_daddr elane_rx_pause_daddr 1652522221569 elane_hi_ber_monitor elane_hi_ber_monitor enable elane_keep_rx_crc elane_keep_rx_crc disable elane_link_fault_mode elane_link_fault_mode lf_off elane_ptp_timestamp_format elane_ptp_timestamp_format v2 elane_ptp_tx_timestamp_method elane_ptp_tx_timestamp_method ptp_1step elane_tx_ptp_extra_latency elane_tx_ptp_extra_latency 0 elane_rx_clock_period elane_rx_clock_period 162689 elane_tx_clock_period elane_tx_clock_period 162689 elane_remove_pads elane_remove_pads disable elane_reset_rx_stats_parity_error elane_reset_rx_stats_parity_error disable elane_reset_tx_stats_parity_error elane_reset_tx_stats_parity_error disable elane_rx_aib_dp_latency elane_rx_aib_dp_latency 0 elane_rx_length_checking elane_rx_length_checking enable elane_rx_vlan_detection elane_rx_vlan_detection enable elane_rx_max_frame_size elane_rx_max_frame_size 1518 elane_rx_pcs_max_skew elane_rx_pcs_max_skew 47 elane_rx_ptp_dp_latency elane_rx_ptp_dp_latency 0 elane_rx_ptp_extra_latency elane_rx_ptp_extra_latency 0 elane_rxcrc_covers_preamble elane_rxcrc_covers_preamble disable elane_strict_preamble_checking elane_strict_preamble_checking disable elane_tx_aib_dp_latency elane_tx_aib_dp_latency 0 elane_tx_pld_fifo_almost_full_level elane_tx_pld_fifo_almost_full_level 16 elane_tx_ptp_asym_latency elane_tx_ptp_asym_latency 0 elane_tx_ptp_dp_latency elane_tx_ptp_dp_latency 0 elane_txcrc_covers_preamble elane_txcrc_covers_preamble disable elane_use_factory_settings elane_use_factory_settings true elane_force_hip_ready elane_force_hip_ready disable elane_force_deskew_done elane_force_deskew_done disable elane_uniform_holdoff_quanta elane_uniform_holdoff_quanta 65535 tx_enable tx_enable 1 rx_enable rx_enable 1 user_enable_serialliteiv user_enable_serialliteiv 0 suppress_design_example_messages suppress_design_example_messages 0 enable_workaround_rules Enable workaround rules 0 design_example_filename Design example filename top rcfg_shared Share reconfiguration interface 0 set_embedded_debug_enable Enable embedded debug 0 validation_rule_select View validation rule for parameter internal_derived_parameter_select View value of internal derived parameter l_is_loopback_mode_enabled rcp_load_enable Enable adaptation load soft IP 0 cal_recipe_sel PMA adaptation Select NRZ_28Gbps_VSR ctle_lf_val_a GAINLF 999 ctle_lf_val_ada_a GAINLF Fix/Adaptable adaptable ctle_lf_min_a CTLE LF Min 999 ctle_lf_max_a CTLE LF Max 999 ctle_hf_val_a GAINHF 999 ctle_hf_val_ada_a GAINHF Fix/Adaptable adaptable ctle_hf_min_a CTLE HF Min 999 ctle_hf_max_a CTLE HF Max 999 rf_p2_val_a RF_P2 999 rf_p2_val_ada_a RF_P2 Fix/Adaptable adaptable rf_p2_min_a RF_P2_MIN 999 rf_p2_max_a RF_P2_MAX 999 rf_p1_val_a RF_P1 999 rf_p1_val_ada_a RF_P1 Fix/Adaptable adaptable rf_p1_min_a RF_P1_MIN 999 rf_p1_max_a RF_P1_MAX 999 rf_reserved0_a Reserved 0 999 rf_p0_val_a RF_P0 999 rf_p0_val_ada_a RF_P0 Fix/Adaptable adaptable rf_reserved1_a Reserved 1 999 rf_b0t_a RF_B0T 999 ctle_gs1_val_a GS1 999 ctle_gs2_val_a GS2 999 rf_b1_a RF_B1 999 rf_b1_ada_a RF_B1 Fix/Adaptable adaptable rf_b0_a RF_B0 999 rf_b0_ada_a RF_B0 Fix/Adaptable adaptable rf_a_a RF_A 999 ctle_lf_val_b GAINLF 999 ctle_lf_val_ada_b GAINLF Fix/Adaptable adaptable ctle_lf_min_b CTLE LF Min 999 ctle_lf_max_b CTLE LF Max 999 ctle_hf_val_b GAINHF 999 ctle_hf_val_ada_b GAINHF Fix/Adaptable adaptable ctle_hf_min_b CTLE HF Min 999 ctle_hf_max_b CTLE HF Max 999 rf_p2_val_b RF_P2 999 rf_p2_val_ada_b RF_P2 Fix/Adaptable adaptable rf_p2_min_b RF_P2_MIN 999 rf_p2_max_b RF_P2_MAX 999 rf_p1_val_b RF_P1 999 rf_p1_val_ada_b RF_P1 Fix/Adaptable adaptable rf_p1_min_b RF_P1_MIN 999 rf_p1_max_b RF_P1_MAX 999 rf_reserved0_b Reserved 0 999 rf_p0_val_b RF_P0 999 rf_p0_val_ada_b RF_P0 Fix/Adaptable adaptable rf_reserved1_b Reserved 1 999 rf_b0t_b RF_B0T 999 ctle_gs1_val_b GS1 999 ctle_gs2_val_b GS2 999 rf_b1_b RF_B1 999 rf_b1_ada_b RF_B1 Fix/Adaptable adaptable rf_b0_b RF_B0 999 rf_b0_ada_b RF_B0 Fix/Adaptable adaptable rf_a_b RF_A 999 adpt_multi_enable Enable multiple PMA configuration 1 adpt_recipe_cnt Number of PMA configuration 1 adpt_recipe_select Select a PMA configuration to load or store 0 adpt_recipe_data0 adpt_recipe_data0 adpt_recipe_data1 adpt_recipe_data1 adpt_recipe_data2 adpt_recipe_data2 adpt_recipe_data3 adpt_recipe_data3 adpt_recipe_data4 adpt_recipe_data4 adpt_recipe_data5 adpt_recipe_data5 adpt_recipe_data6 adpt_recipe_data6 adpt_recipe_data7 adpt_recipe_data7 rcfg_debug rcfg_debug 0 rcfg_enable Enable dynamic reconfiguration 0 rcfg_jtag_enable Enable Native PHY Debug Master Endpoint 0 rcfg_separate_avmm_busy Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE 0 rcfg_enable_avmm_busy_port Enable avmm_busy port 0 set_capability_reg_enable Enable capability registers 0 set_user_identifier Set user-defined IP identifier 0 set_csr_soft_logic_enable Enable control and status registers 0 rcfg_file_prefix Configuration file prefix altera_xcvr_rcfg_10 rcfg_files_as_common_package Declare SystemVerilog package file as common package file 0 rcfg_sv_file_enable Generate SystemVerilog package file 0 rcfg_h_file_enable Generate C header file 0 rcfg_txt_file_enable Generate text file 0 rcfg_mif_file_enable Generate MIF (Memory Initialize File) 0 rcfg_multi_enable Enable multiple reconfiguration profiles 0 set_rcfg_emb_strm_enable Enable embedded reconfiguration streamer 0 rcfg_reduced_files_enable Generate reduced reconfiguration files 0 rcfg_profile_cnt Number of reconfiguration profiles 2 rcfg_profile_select Store current configuration to profile: 1 rcfg_profile_data0 rcfg_profile_data0 rcfg_profile_data1 rcfg_profile_data1 rcfg_profile_data2 rcfg_profile_data2 rcfg_profile_data3 rcfg_profile_data3 rcfg_profile_data4 rcfg_profile_data4 rcfg_profile_data5 rcfg_profile_data5 rcfg_profile_data6 rcfg_profile_data6 rcfg_profile_data7 rcfg_profile_data7 rcfg_sdc_derived_profile_data0 rcfg_sdc_derived_profile_data0 rcfg_sdc_derived_profile_data1 rcfg_sdc_derived_profile_data1 rcfg_sdc_derived_profile_data2 rcfg_sdc_derived_profile_data2 rcfg_sdc_derived_profile_data3 rcfg_sdc_derived_profile_data3 rcfg_sdc_derived_profile_data4 rcfg_sdc_derived_profile_data4 rcfg_sdc_derived_profile_data5 rcfg_sdc_derived_profile_data5 rcfg_sdc_derived_profile_data6 rcfg_sdc_derived_profile_data6 rcfg_sdc_derived_profile_data7 rcfg_sdc_derived_profile_data7 enable_custom_backplane_mode_checkbox Enable Custom Backplane Mode options 0 enable_rsfec_support_mode_options_checkbox Enable RSFEC support mode options 0 support_mode_rsfec RSFEC support mode advanced_user_mode aggregate_rsfec_enable_checkbox Enable aggregate mode 0 l_hssi_rsfec_clocking_mode RSFEC Clocking Mode fec_dir_adp_clk_0 l_hssi_rsfec_first_lane_sel First RSFEC Lane first_lane0 l_hssi_rsfec_source_lane_ena0 Source Lane Enable Lane 0 0 l_hssi_rsfec_source_lane_ena1 Source Lane Enable Lane 1 0 l_hssi_rsfec_source_lane_ena2 Source Lane Enable Lane 2 0 l_hssi_rsfec_source_lane_ena3 Source Lane Enable Lane 3 0 l_hssi_rsfec_tx_data_source_sel0 TX Data Source Lane 0 fec_tx_lane_off0 l_hssi_rsfec_tx_data_source_sel1 TX Data Source Lane 1 fec_tx_lane_off1 l_hssi_rsfec_tx_data_source_sel2 TX Data Source Lane 2 fec_tx_lane_off2 l_hssi_rsfec_tx_data_source_sel3 TX Data Source Lane 3 fec_tx_lane_off3 l_hssi_rsfec_core_fibre_channel0_string Alignment/Scrambling/Transcoder Mode Lane 0 Basic Mode l_hssi_rsfec_core_fibre_channel1_string Alignment/Scrambling/Transcoder Mode Lane 1 Basic Mode l_hssi_rsfec_core_fibre_channel2_string Alignment/Scrambling/Transcoder Mode Lane 2 Basic Mode l_hssi_rsfec_core_fibre_channel3_string Alignment/Scrambling/Transcoder Mode Lane 3 Basic Mode l_hssi_rsfec_core_eng_trans_byp0_string Transcoder Bypass Lane 0 Enabled l_hssi_rsfec_core_eng_trans_byp1_string Transcoder Bypass Lane 1 Enabled l_hssi_rsfec_core_eng_trans_byp2_string Transcoder Bypass Lane 2 Enabled l_hssi_rsfec_core_eng_trans_byp3_string Transcoder Bypass Lane 3 Enabled l_hssi_rsfec_core_eng_swaps0 core_eng_swaps Lane 0 0 l_hssi_rsfec_core_eng_swaps1 core_eng_swaps Lane 1 0 l_hssi_rsfec_core_eng_swaps2 core_eng_swaps Lane 2 0 l_hssi_rsfec_core_eng_swaps3 core_eng_swaps Lane 3 0 l_hssi_rsfec_fec_tx2rx_loopback0 TX to RX Loopback Lane 0 0 l_hssi_rsfec_fec_tx2rx_loopback1 TX to RX Loopback Lane 1 0 l_hssi_rsfec_fec_tx2rx_loopback2 TX to RX Loopback Lane 2 0 l_hssi_rsfec_fec_tx2rx_loopback3 TX to RX Loopback Lane 3 0 l_hssi_rsfec_force_deskew_done Force Deskew Done Output 0 l_hssi_rsfec_force_fec_ready Force FEC Ready Output 0 l_hssi_rsfec_deskew_channels_clear Deskew Channels Clear (Reset) 0 l_hssi_rsfec_core_eng_enter_align_entry_field core_eng_enter_align 0 l_hssi_rsfec_core_eng_exit_align_entry_field core_eng_exit_align 0 l_hssi_rsfec_core_eng_test core_eng_test 0 l_hssi_rsfec_core_indic_byp0 core_indic_byp Lane 0 0 l_hssi_rsfec_core_indic_byp1 core_indic_byp Lane 1 0 l_hssi_rsfec_core_indic_byp2 core_indic_byp Lane 2 0 l_hssi_rsfec_core_indic_byp3 core_indic_byp Lane 3 0 l_hssi_rsfec_core_eng_sf_dis0 core_eng_sf_dis Lane 0 0 l_hssi_rsfec_core_eng_fec_3bad_dis0 core_eng_fec_3bad_dis Lane 0 0 l_hssi_rsfec_core_eng_am_5bad_dis0 core_eng_am_5bad_dis Lane 0 0 l_hssi_rsfec_core_eng_blk_chk_dis0 core_eng_blk_chk_dis Lane 0 0 l_hssi_rsfec_core_eng_sf_dis1 core_eng_sf_dis Lane 1 0 l_hssi_rsfec_core_eng_fec_3bad_dis1 core_eng_fec_3bad_dis Lane 1 0 l_hssi_rsfec_core_eng_am_5bad_dis1 core_eng_am_5bad_dis Lane 1 0 l_hssi_rsfec_core_eng_blk_chk_dis1 core_eng_blk_chk_dis Lane 1 0 l_hssi_rsfec_core_eng_sf_dis2 core_eng_sf_dis Lane 2 0 l_hssi_rsfec_core_eng_fec_3bad_dis2 core_eng_fec_3bad_dis Lane 2 0 l_hssi_rsfec_core_eng_am_5bad_dis2 core_eng_am_5bad_dis Lane 2 0 l_hssi_rsfec_core_eng_blk_chk_dis2 core_eng_blk_chk_dis Lane 2 0 l_hssi_rsfec_core_eng_sf_dis3 core_eng_sf_dis Lane 3 0 l_hssi_rsfec_core_eng_fec_3bad_dis3 core_eng_fec_3bad_dis Lane 3 0 l_hssi_rsfec_core_eng_am_5bad_dis3 core_eng_am_5bad_dis Lane 3 0 l_hssi_rsfec_core_eng_blk_chk_dis3 core_eng_blk_chk_dis Lane 3 0 l_hssi_rsfecrx_mux_rx_data_source RX Mux Data Source fec_rx_data l_enable_reset_controller Enable automatic reset control 0 device Device AGFB014R24B2E2V deviceFamily Device family Agilex deviceSpeedGrade Device Speed Grade 2 generationId Generation Id 0 bonusData bonusData bonusData { element xcvrnphy_fme_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> false false