// ---------------------------------------------------------------------- // "THE BEER-WARE LICENSE" (Revision 42): // wrote this file. As long as you retain this // notice you can do whatever you want with this stuff. If we meet // some day, and you think this stuff is worth it, you can buy me a // beer in return Yasunori Osana at University of the Ryukyus, // Japan. // ---------------------------------------------------------------------- // OpenFC project: an open FPGA accelerated cluster toolkit // Kyokko project: an open Multi-vendor Aurora 64B/66B-compatible link // // Modules in this file: // c10gx_kyokko: Kyokko + Transceiver wrapper for Cyclone 10 GX Dev board // ---------------------------------------------------------------------- `default_nettype none module c10gx_kyokko # ( parameter NumCh=2 ) ( input wire CLK100, RST, input wire CLK644P, output wire [1:0] SFP_TXP, SFP_TXN, input wire [1:0] SFP_RXP, SFP_RXN, // ------------------------------ // Aurora compatible interface signals output wire [NumCh-1:0] CH_UP, USER_CLK, // Data channel input wire [64*NumCh-1:0] S_AXI_TX_TDATA, input wire [ NumCh-1:0] S_AXI_TX_TLAST, S_AXI_TX_TVALID, output wire [NumCh-1:0] S_AXI_TX_TREADY, output wire [64*NumCh-1:0] M_AXI_RX_TDATA, output wire [ NumCh-1:0] M_AXI_RX_TLAST, M_AXI_RX_TVALID, // UFC channel input wire [NumCh-1:0] UFC_TX_REQ, input wire [8*NumCh-1:0] UFC_TX_MS, input wire [64*NumCh-1:0] S_AXI_UFC_TX_TDATA, input wire [NumCh-1:0] S_AXI_UFC_TX_TVALID, output wire [NumCh-1:0] S_AXI_UFC_TX_TREADY, output wire [64*NumCh-1:0] M_AXI_UFC_RX_TDATA, output wire [ NumCh-1:0] M_AXI_UFC_RX_TLAST, M_AXI_UFC_RX_TVALID, // NFC channel input wire [16*NumCh-1:0] S_AXI_NFC_TDATA, input wire [NumCh-1:0] S_AXI_NFC_TVALID, output wire [NumCh-1:0] S_AXI_NFC_TREADY ); wire GT_RST; gt_rst grst ( .CLK(CLK100), .RST(RST), .GT_RST(GT_RST) ); // ------------------------------ // Kyokko instances wire PLL_LOCKED; wire [NumCh-1:0] RX_LOCKED; wire [NumCh-1:0] TXUSERCLK2; wire [NumCh-1:0] RXUSERCLK2; wire [63:0] TXS [NumCh-1:0], RXS [NumCh-1:0]; wire [1:0] TXHDRi [NumCh-1:0]; wire [1:0] RXHDRi [NumCh-1:0]; wire [NumCh-1:0] RXRST = ~RX_LOCKED; wire [NumCh-1:0] TXRST = ~{NumCh{PLL_LOCKED}}; wire [NumCh-1:0] RXPATH_RST, RXSLIP; assign USER_CLK = TXUSERCLK2; genvar ch; generate for (ch=0; ch