xilinx.com xci unknown 1.0 fifo_66x512_async 100000000 0 0 0.000 100000000 0 0 0.000 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 100000000 0 0 0.000 100000000 0 0 0.000 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.000 0 0 0 0 100000000 0 0 0.000 0 0 0 0 0 0 0 8 1 1 1 1 4 0 32 1 1 1 64 1 8 1 1 1 1 0 0 9 BlankString 66 1 32 64 1 64 2 0 66 0 1 1 0 0 0 0 0 0 0 virtexuplus 1 1 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 1 1 1 1 1 0 0 1 BlankString 1 0 0 0 2 1 512x72 1kx18 512x36 512x72 512x36 512x72 512x36 2 1022 1022 1022 1022 1022 1022 3 0 0 0 0 0 0 0 509 1023 1023 1023 1023 1023 1023 508 0 0 0 0 0 0 0 0 0 9 512 1 9 0 0 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 9 512 1024 16 1024 16 1024 16 1 9 10 4 10 4 10 4 1 32 0 0 false true false 0 0 Slave_Interface_Clock_Enable Common_Clock fifo_66x512_async 64 false 9 false false 0 2 1022 1022 1022 1022 1022 1022 3 false false false false false false false false false Hard_ECC false false false false false false true true false true Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Independent_Clocks_Block_RAM 1 509 1023 1023 1023 1023 1023 1023 508 false false false 0 Native false false false false false false false false false false false false false false 66 512 1024 16 1024 16 1024 16 false 66 512 Embedded_Reg false false Active_High Active_High AXI4 Standard_FIFO No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold READ_WRITE 0 1 false 9 Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered true Asynchronous_Reset false 1 0 0 1 1 4 false false Active_High Active_High true true false false true Active_High 0 false Active_High 1 false 9 false FIFO false false false false FIFO FIFO 2 2 false FIFO FIFO FIFO virtexuplus xcu200 fsgd2104 VERILOG VERILOG -2 E TRUE TRUE IP_Flow 5 TRUE . . 2020.1.1_AR75516 OUT_OF_CONTEXT