Intel Corporation atx_12g xcvr_atx_pll_s10_htile_0 19.1 pll_refclk0 clk pll_refclk0 clockRate Clock rate 0 externallyDriven Externally driven false ptfSchematicName PTF schematic name ui.blockdiagram.direction input tx_serial_clk_gxt clk tx_serial_clk_gxt clockRate Clock rate 0 ui.blockdiagram.direction output pll_locked pll_locked pll_locked associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output pll_cal_busy pll_cal_busy pll_cal_busy associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH altera_xcvr_atx_pll_s10_htile QUARTUS_SYNTH pll_refclk0 in STD_LOGIC QUARTUS_SYNTH tx_serial_clk_gxt out STD_LOGIC QUARTUS_SYNTH pll_locked out STD_LOGIC QUARTUS_SYNTH pll_cal_busy out STD_LOGIC QUARTUS_SYNTH Intel Corporation atx_12g altera_xcvr_atx_pll_s10_htile 19.1 rcfg_debug rcfg_debug 0 enable_multi_profile enable_multi_profile 1 rcfg_enable Enable dynamic reconfiguration 0 enable_advanced_avmm_options enable_advanced_avmm_options 0 rcfg_jtag_enable Enable Native PHY Debug Master Endpoint 0 rcfg_separate_avmm_busy Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE 0 rcfg_enable_avmm_busy_port Enable avmm_busy port 0 set_capability_reg_enable Enable capability registers 0 set_user_identifier Set user-defined IP identifier 0 set_csr_soft_logic_enable Enable control and status registers 0 dbg_embedded_debug_enable dbg_embedded_debug_enable 0 dbg_capability_reg_enable dbg_capability_reg_enable 0 dbg_user_identifier dbg_user_identifier 0 dbg_stat_soft_logic_enable dbg_stat_soft_logic_enable 0 dbg_ctrl_soft_logic_enable dbg_ctrl_soft_logic_enable 0 rcfg_file_prefix Configuration file prefix altera_xcvr_atx_pll_s10 rcfg_files_as_common_package Declare SystemVerilog package file as common package file 0 rcfg_sv_file_enable Generate SystemVerilog package file 0 rcfg_h_file_enable Generate C header file 0 rcfg_txt_file_enable Generate text file 0 rcfg_mif_file_enable Generate MIF (Memory Initialize File) 0 rcfg_multi_enable Enable multiple reconfiguration profiles 0 set_rcfg_emb_strm_enable Enable embedded reconfiguration streamer 0 rcfg_emb_strm_enable rcfg_emb_strm_enable 0 rcfg_reduced_files_enable Generate reduced reconfiguration files 0 rcfg_profile_cnt Number of reconfiguration profiles 2 rcfg_profile_select Store current configuration to profile: 1 rcfg_profile_data0 rcfg_profile_data0 rcfg_profile_data1 rcfg_profile_data1 rcfg_profile_data2 rcfg_profile_data2 rcfg_profile_data3 rcfg_profile_data3 rcfg_profile_data4 rcfg_profile_data4 rcfg_profile_data5 rcfg_profile_data5 rcfg_profile_data6 rcfg_profile_data6 rcfg_profile_data7 rcfg_profile_data7 rcfg_sdc_derived_profile_data0 rcfg_sdc_derived_profile_data0 rcfg_sdc_derived_profile_data1 rcfg_sdc_derived_profile_data1 rcfg_sdc_derived_profile_data2 rcfg_sdc_derived_profile_data2 rcfg_sdc_derived_profile_data3 rcfg_sdc_derived_profile_data3 rcfg_sdc_derived_profile_data4 rcfg_sdc_derived_profile_data4 rcfg_sdc_derived_profile_data5 rcfg_sdc_derived_profile_data5 rcfg_sdc_derived_profile_data6 rcfg_sdc_derived_profile_data6 rcfg_sdc_derived_profile_data7 rcfg_sdc_derived_profile_data7 rcfg_params rcfg_params rcfg_debug,rcfg_enable,rcfg_jtag_enable,rcfg_separate_avmm_busy,rcfg_enable_avmm_busy_port,set_capability_reg_enable,set_user_identifier,set_csr_soft_logic_enable,enable_pld_atx_cal_busy_port,support_mode,prot_mode,bw_sel,refclk_cnt,refclk_index,primary_pll_buffer,enable_8G_path,enable_28G_output_frm_abv_atx,enable_28G_output_frm_blw_atx,enable_28G_local_atx_path,enable_28G_input_frm_abv_atx,enable_28G_input_frm_blw_atx,enable_GXT_out_buffer_abv,enable_GXT_out_buffer_blw,enable_GXT_clock_source,enable_pcie_clk,enable_cascade_out,enable_hip_cal_done_port,set_hip_cal_en,set_output_clock_frequency,set_auto_reference_clock_frequency,set_manual_reference_clock_frequency,set_fref_clock_frequency,set_m_counter,set_ref_clk_div,set_l_counter,set_l_cascade_counter,set_l_cascade_predivider,set_k_counter,enable_mcgb,mcgb_div,enable_hfreq_clk,enable_mcgb_pcie_clksw,enable_mcgb_reset,mcgb_aux_clkin_cnt,enable_bonding_clks,enable_fb_comp_bonding,pma_width,enable_pld_mcgb_cal_busy_port rcfg_param_labels IP Parameters rcfg_debug,Enable dynamic reconfiguration,Enable Native PHY Debug Master Endpoint,Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE,Enable avmm_busy port,Enable capability registers,Set user-defined IP identifier,Enable control and status registers,enable_pld_atx_cal_busy_port,Support mode,Protocol mode,Bandwidth,Number of PLL reference clocks,Selected reference clock source,Primary PLL clock output buffer,Enable GX clock output port (tx_serial_clk),Enable GXT clock output port to above ATX PLL (gxt_output_to_abv_atx),Enable GXT clock output port to below ATX PLL (gxt_output_to_blw_atx),Enable GXT local clock output port (tx_serial_clk_gxt),Enable GXT clock input port from above ATX PLL (gxt_input_from_abv_atx),Enable GXT clock input port from below ATX PLL (gxt_input_from_blw_atx),Enable GXT clock buffer to above ATX PLL,Enable GXT clock buffer to below ATX PLL,GXT output clock source,Enable PCIe clock output port,Enable cascade clock output port,Enable calibration status ports for HIP,Enable PCIe hard IP calibration,PLL output frequency,PLL auto mode reference clock frequency (Integer),PLL manual mode reference clock frequency,PLL auto mode reference clock frequency (Fractional),Multiply factor (M-Counter),Divide factor (N-Counter),Divide factor (L-Counter),Divide factor (L-Cascade Counter),Divide factor (L-Cascade-Predivider),Fractional multiply factor (K),Include Master Clock Generation Block,Clock division factor,Enable x24 non-bonded high-speed clock output port,Enable PCIe clock switch interface,Enable mcgb_rst and mcgb_rst_stat ports,Number of auxiliary MCGB clock input ports.,Enable bonding clock output ports,Enable feedback compensation bonding,PMA interface width,enable_pld_mcgb_cal_busy_port rcfg_param_vals0 Profile 0 rcfg_param_vals1 Profile 1 rcfg_param_vals2 Profile 2 rcfg_param_vals3 Profile 3 rcfg_param_vals4 Profile 4 rcfg_param_vals5 Profile 5 rcfg_param_vals6 Profile 6 rcfg_param_vals7 Profile 7 rcfg_sdc_derived_params rcfg_sdc_derived_params enable_multi_profile,dbg_embedded_debug_enable,dbg_capability_reg_enable,dbg_user_identifier,dbg_stat_soft_logic_enable,dbg_ctrl_soft_logic_enable,atx_pll_lcpll_gt_in_sel,atx_pll_lcpll_gt_out_left_enb,atx_pll_lcpll_gt_out_mid_enb,atx_pll_lcpll_gt_out_right_enb,enable_atx_to_fpll_cascade_out,output_clock_datarate,datarate,enable_fractional rcfg_sdc_derived_param_vals0 rcfg_sdc_derived_param_vals0 rcfg_sdc_derived_param_vals1 rcfg_sdc_derived_param_vals1 rcfg_sdc_derived_param_vals2 rcfg_sdc_derived_param_vals2 rcfg_sdc_derived_param_vals3 rcfg_sdc_derived_param_vals3 rcfg_sdc_derived_param_vals4 rcfg_sdc_derived_param_vals4 rcfg_sdc_derived_param_vals5 rcfg_sdc_derived_param_vals5 rcfg_sdc_derived_param_vals6 rcfg_sdc_derived_param_vals6 rcfg_sdc_derived_param_vals7 rcfg_sdc_derived_param_vals7 hssi_avmm2_if_pcs_arbiter_ctrl hssi_avmm2_if_pcs_arbiter_ctrl avmm2_arbiter_uc_sel hssi_avmm2_if_hssiadapt_avmm_clk_dcg_en hssi_avmm2_if_hssiadapt_avmm_clk_dcg_en disable hssi_avmm2_if_hssiadapt_avmm_clk_scg_en hssi_avmm2_if_hssiadapt_avmm_clk_scg_en disable hssi_avmm2_if_pldadapt_avmm_clk_scg_en hssi_avmm2_if_pldadapt_avmm_clk_scg_en disable hssi_avmm2_if_pcs_cal_done hssi_avmm2_if_pcs_cal_done avmm2_cal_done_deassert hssi_avmm2_if_pcs_cal_reserved hssi_avmm2_if_pcs_cal_reserved 0 hssi_avmm2_if_pcs_calibration_feature_en hssi_avmm2_if_pcs_calibration_feature_en avmm2_pcs_calibration_en hssi_avmm2_if_pldadapt_gate_dis hssi_avmm2_if_pldadapt_gate_dis disable hssi_avmm2_if_pcs_hip_cal_en hssi_avmm2_if_pcs_hip_cal_en disable hssi_avmm2_if_hssiadapt_osc_clk_scg_en hssi_avmm2_if_hssiadapt_osc_clk_scg_en disable hssi_avmm2_if_pldadapt_osc_clk_scg_en hssi_avmm2_if_pldadapt_osc_clk_scg_en disable hssi_avmm2_if_hssiadapt_avmm_osc_clock_setting hssi_avmm2_if_hssiadapt_avmm_osc_clock_setting osc_clk_div_by1 hssi_avmm2_if_pldadapt_avmm_osc_clock_setting hssi_avmm2_if_pldadapt_avmm_osc_clock_setting osc_clk_div_by1 hssi_avmm2_if_hssiadapt_avmm_testbus_sel hssi_avmm2_if_hssiadapt_avmm_testbus_sel avmm1_transfer_testbus hssi_avmm2_if_pldadapt_avmm_testbus_sel hssi_avmm2_if_pldadapt_avmm_testbus_sel avmm1_transfer_testbus hssi_avmm2_if_func_mode hssi_avmm2_if_func_mode c3adpt_pmadir hssi_avmm2_if_hssiadapt_hip_mode hssi_avmm2_if_hssiadapt_hip_mode disable_hip hssi_avmm2_if_pldadapt_hip_mode hssi_avmm2_if_pldadapt_hip_mode disable_hip hssi_avmm2_if_topology hssi_avmm2_if_topology disabled_block hssi_avmm2_if_silicon_rev hssi_avmm2_if_silicon_rev 14nm5bcr2eb hssi_avmm2_if_calibration_type hssi_avmm2_if_calibration_type one_time atx_pll_analog_mode atx_pll_analog_mode user_custom atx_pll_bandwidth_range_high atx_pll_bandwidth_range_high 1 atx_pll_bandwidth_range_low atx_pll_bandwidth_range_low 1 atx_pll_bonding atx_pll_bonding cpri_bonding atx_pll_bw_mode atx_pll_bw_mode high_bw atx_pll_cal_status atx_pll_cal_status cal_in_progress atx_pll_calibration_mode atx_pll_calibration_mode cal_off atx_pll_cascadeclk_test atx_pll_cascadeclk_test cascadetest_off atx_pll_cgb_div atx_pll_cgb_div 1 atx_pll_chgpmp_testmode atx_pll_chgpmp_testmode cp_normal atx_pll_clk_high_perf_voltage atx_pll_clk_high_perf_voltage 0 atx_pll_clk_low_power_voltage atx_pll_clk_low_power_voltage 0 atx_pll_clk_mid_power_voltage atx_pll_clk_mid_power_voltage 0 atx_pll_datarate_bps Datarate 25781250000 atx_pll_device_variant atx_pll_device_variant device_off atx_pll_clk_vreg_boost_expected_voltage atx_pll_clk_vreg_boost_expected_voltage 0 atx_pll_clk_vreg_boost_scratch atx_pll_clk_vreg_boost_scratch 0 atx_pll_clk_vreg_boost_step_size atx_pll_clk_vreg_boost_step_size 0 atx_pll_lc_vreg1_boost_expected_voltage atx_pll_lc_vreg1_boost_expected_voltage 0 atx_pll_lc_vreg1_boost_scratch atx_pll_lc_vreg1_boost_scratch 0 atx_pll_lc_vreg_boost_expected_voltage atx_pll_lc_vreg_boost_expected_voltage 0 atx_pll_lc_vreg_boost_scratch atx_pll_lc_vreg_boost_scratch 0 atx_pll_mcgb_vreg_boost_expected_voltage atx_pll_mcgb_vreg_boost_expected_voltage 0 atx_pll_mcgb_vreg_boost_scratch atx_pll_mcgb_vreg_boost_scratch 0 atx_pll_mcgb_vreg_boost_step_size atx_pll_mcgb_vreg_boost_step_size 0 atx_pll_pm_dprio_lc_dprio_status_select atx_pll_pm_dprio_lc_dprio_status_select dprio_normal_status atx_pll_vreg1_boost_step_size atx_pll_vreg1_boost_step_size 0 atx_pll_vreg_boost_step_size atx_pll_vreg_boost_step_size 0 atx_pll_enable_hclk atx_pll_enable_hclk false atx_pll_expected_lc_boost_voltage atx_pll_expected_lc_boost_voltage 0 atx_pll_f_max_lcnt_fpll_cascading atx_pll_f_max_lcnt_fpll_cascading 1200000000 atx_pll_f_max_pfd atx_pll_f_max_pfd 800000000 atx_pll_f_max_pfd_fractional atx_pll_f_max_pfd_fractional 1 atx_pll_f_max_ref atx_pll_f_max_ref 800000000 atx_pll_f_max_tank_0 atx_pll_f_max_tank_0 8800000000 atx_pll_f_max_tank_1 atx_pll_f_max_tank_1 11400000000 atx_pll_f_max_tank_2 atx_pll_f_max_tank_2 14400000000 atx_pll_f_max_vco atx_pll_f_max_vco 14400000000 atx_pll_f_max_vco_fractional atx_pll_f_max_vco_fractional 1 atx_pll_f_max_x1 atx_pll_f_max_x1 8700000000 atx_pll_f_min_pfd atx_pll_f_min_pfd 61440000 atx_pll_f_min_ref atx_pll_f_min_ref 61440000 atx_pll_f_min_tank_0 atx_pll_f_min_tank_0 6500000000 atx_pll_f_min_tank_1 atx_pll_f_min_tank_1 8800000000 atx_pll_f_min_tank_2 atx_pll_f_min_tank_2 11400000000 atx_pll_f_min_vco atx_pll_f_min_vco 7200000000 atx_pll_fpll_refclk_selection L cascade predivider/VCO divider(valid in cascade mode) select_vco_output atx_pll_hclk_en atx_pll_hclk_en hclk_disabled atx_pll_initial_settings atx_pll_initial_settings true atx_pll_is_otn atx_pll_is_otn false atx_pll_is_sdi atx_pll_is_sdi false atx_pll_l_counter L counter (valid in non-cascade mode) 1 atx_pll_lc_cal_reserved atx_pll_lc_cal_reserved lc_cal_reserved_off atx_pll_lc_cal_status atx_pll_lc_cal_status lc_status_notdone atx_pll_lc_calibration atx_pll_lc_calibration lc_cal_on atx_pll_lc_dyn_reconfig atx_pll_lc_dyn_reconfig lc_dyn_reconfig_off atx_pll_lc_reg_calibration atx_pll_lc_reg_calibration lc_uccal_reg_off atx_pll_lc_reg_status atx_pll_lc_reg_status lc_reg_sta_off atx_pll_lc_to_fpll_l_counter atx_pll_lc_to_fpll_l_counter lcounter_setting0 atx_pll_lc_to_fpll_l_counter_scratch L cascade counter (valid in cascade mode) 0 atx_pll_lc_vreg1_boost atx_pll_lc_vreg1_boost lc_vreg1_off atx_pll_lc_vreg_boost atx_pll_lc_vreg_boost lc_vreg_off atx_pll_lccmu_mode atx_pll_lccmu_mode lccmu_normal atx_pll_lcpll_gt_in_sel atx_pll_lcpll_gt_in_sel lc_gt_in_sel3 atx_pll_lcpll_gt_out_left_enb atx_pll_lcpll_gt_out_left_enb lcpll_gt_out_left_dis atx_pll_lcpll_gt_out_mid_enb atx_pll_lcpll_gt_out_mid_enb lcpll_gt_out_mid_dis atx_pll_lcpll_gt_out_right_enb atx_pll_lcpll_gt_out_right_enb lcpll_gt_out_right_dis atx_pll_lcpll_lckdet_sel atx_pll_lcpll_lckdet_sel lc_lckdet_sel0 atx_pll_max_fractional_percentage atx_pll_max_fractional_percentage 100 atx_pll_mcnt_divide M counter 10 atx_pll_min_fractional_percentage atx_pll_min_fractional_percentage 0 atx_pll_n_counter atx_pll_n_counter 1 atx_pll_out_freq atx_pll_out_freq 12890625000 atx_pll_pfd_delay_compensation atx_pll_pfd_delay_compensation normal_delay atx_pll_pfd_pulse_width atx_pll_pfd_pulse_width pulse_width_setting0 atx_pll_pma_width atx_pll_pma_width 64 atx_pll_power_mode atx_pll_power_mode mid_power atx_pll_power_rail_et atx_pll_power_rail_et 1030 atx_pll_powerdown_mode atx_pll_powerdown_mode powerup_off atx_pll_powermode_ac_lc atx_pll_powermode_ac_lc lc2_ac_div1 atx_pll_powermode_ac_lc_gtpath atx_pll_powermode_ac_lc_gtpath lc_gt_ac_off atx_pll_powermode_dc_lc atx_pll_powermode_dc_lc lc2_dc_div1 atx_pll_powermode_dc_lc_gtpath atx_pll_powermode_dc_lc_gtpath powerdown_lc_gt atx_pll_primary_use atx_pll_primary_use hssi_hf atx_pll_prot_mode atx_pll_prot_mode basic_tx atx_pll_reference_clock_frequency atx_pll_reference_clock_frequency 644531250 atx_pll_regulator_bypass atx_pll_regulator_bypass reg_enable atx_pll_side atx_pll_side side_off atx_pll_bcm_silicon_rev atx_pll_bcm_silicon_rev rev_off atx_pll_speed_grade atx_pll_speed_grade e2 atx_pll_sup_mode atx_pll_sup_mode user_mode atx_pll_top_or_bottom atx_pll_top_or_bottom top_or_bot_off atx_pll_vccdreg_clk atx_pll_vccdreg_clk vreg_clk5 atx_pll_vccdreg_fb atx_pll_vccdreg_fb vreg_fb0 atx_pll_vccdreg_fw atx_pll_vccdreg_fw vreg_fw5 atx_pll_vco_freq VCO Frequency 12890625000 atx_pll_xatb_lccmu_atb atx_pll_xatb_lccmu_atb atb_selectdisable atx_pll_chgpmp_compensation atx_pll_chgpmp_compensation cp_mode_enable atx_pll_chgpmp_current_setting atx_pll_chgpmp_current_setting cp_current_setting33 atx_pll_cp_current_boost atx_pll_cp_current_boost normal_setting atx_pll_lf_3rd_pole_freq atx_pll_lf_3rd_pole_freq lf_3rd_pole_setting0 atx_pll_lf_cbig_size atx_pll_lf_cbig_size lf_cbig_setting4 atx_pll_lf_order atx_pll_lf_order lf_2nd_order atx_pll_lf_resistance atx_pll_lf_resistance lf_setting0 atx_pll_lf_ripplecap atx_pll_lf_ripplecap lf_no_ripple atx_pll_lc_sel_tank atx_pll_lc_sel_tank lctank2 atx_pll_lc_tank_band atx_pll_lc_tank_band lc_band5 atx_pll_lc_tank_voltage_coarse atx_pll_lc_tank_voltage_coarse vreg_setting_coarse0 atx_pll_lc_tank_voltage_fine atx_pll_lc_tank_voltage_fine vreg_setting5 atx_pll_output_regulator_supply atx_pll_output_regulator_supply vreg1v_setting0 atx_pll_overrange_voltage atx_pll_overrange_voltage over_setting0 atx_pll_underrange_voltage atx_pll_underrange_voltage under_setting4 atx_pll_xd2a_lc_d2a_voltage atx_pll_xd2a_lc_d2a_voltage d2a_setting_4 atx_pll_dsm_mode atx_pll_dsm_mode dsm_mode_integer atx_pll_pll_dsm_out_sel atx_pll_pll_dsm_out_sel pll_dsm_disable atx_pll_pll_ecn_bypass atx_pll_pll_ecn_bypass pll_ecn_bypass_disable atx_pll_pll_ecn_test_en atx_pll_pll_ecn_test_en pll_ecn_test_disable atx_pll_dsm_fractional_division K counter (valid in fractional mode) 1 atx_pll_pll_fractional_value_ready atx_pll_pll_fractional_value_ready pll_k_ready atx_pll_direct_fb atx_pll_direct_fb direct_fb atx_pll_iqclk_sel atx_pll_iqclk_sel iqtxrxclk0 atx_pll_lcnt_bypass atx_pll_lcnt_bypass lcnt_no_bypass atx_pll_lcnt_divide atx_pll_lcnt_divide 1 atx_pll_lcnt_off atx_pll_lcnt_off lcnt_off atx_pll_ref_clk_div N counter 1 atx_pll_silicon_rev atx_pll_silicon_rev 14nm5bcr2eb atx_pll_is_cascaded_pll atx_pll_is_cascaded_pll false hssi_pma_lc_refclk_select_mux_lc_iq_scratch0_src hssi_pma_lc_refclk_select_mux_lc_iq_scratch0_src scratch0_power_down hssi_pma_lc_refclk_select_mux_lc_iq_scratch1_src hssi_pma_lc_refclk_select_mux_lc_iq_scratch1_src scratch1_power_down hssi_pma_lc_refclk_select_mux_lc_iq_scratch2_src hssi_pma_lc_refclk_select_mux_lc_iq_scratch2_src scratch2_power_down hssi_pma_lc_refclk_select_mux_lc_iq_scratch3_src hssi_pma_lc_refclk_select_mux_lc_iq_scratch3_src scratch3_power_down hssi_pma_lc_refclk_select_mux_lc_iq_scratch4_src hssi_pma_lc_refclk_select_mux_lc_iq_scratch4_src scratch4_power_down hssi_pma_lc_refclk_select_mux_lc_scratch0_src hssi_pma_lc_refclk_select_mux_lc_scratch0_src scratch0_src_lvpecl hssi_pma_lc_refclk_select_mux_lc_scratch1_src hssi_pma_lc_refclk_select_mux_lc_scratch1_src scratch1_src_lvpecl hssi_pma_lc_refclk_select_mux_lc_scratch2_src hssi_pma_lc_refclk_select_mux_lc_scratch2_src scratch2_src_lvpecl hssi_pma_lc_refclk_select_mux_lc_scratch3_src hssi_pma_lc_refclk_select_mux_lc_scratch3_src scratch3_src_lvpecl hssi_pma_lc_refclk_select_mux_lc_scratch4_src hssi_pma_lc_refclk_select_mux_lc_scratch4_src scratch4_src_lvpecl hssi_pma_lc_refclk_select_mux_xpll_lccmu_mode hssi_pma_lc_refclk_select_mux_xpll_lccmu_mode lccmu_normal hssi_pma_lc_refclk_select_mux_powerdown_mode hssi_pma_lc_refclk_select_mux_powerdown_mode powerup hssi_pma_lc_refclk_select_mux_xmux_refclk_src hssi_pma_lc_refclk_select_mux_xmux_refclk_src src_coreclk hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_iqclk_sel hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_iqclk_sel iqtxrxclk0 hssi_pma_lc_refclk_select_mux_silicon_rev hssi_pma_lc_refclk_select_mux_silicon_rev 14nm5bcr2eb hssi_pma_lc_refclk_select_mux_refclk_select hssi_pma_lc_refclk_select_mux_refclk_select ref_iqclk0 hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping ref_iqclk0 hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping power_down hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping power_down hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping power_down hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping power_down hssi_refclk_divider_clk_divider hssi_refclk_divider_clk_divider div2_off hssi_refclk_divider_clkbuf_sel hssi_refclk_divider_clkbuf_sel high_vcm hssi_refclk_divider_core_clk_lvpecl hssi_refclk_divider_core_clk_lvpecl core_clk_lvpecl_off hssi_refclk_divider_enable_lvpecl hssi_refclk_divider_enable_lvpecl lvpecl_enable hssi_refclk_divider_iostandard hssi_refclk_divider_iostandard io_off hssi_refclk_divider_optimal hssi_refclk_divider_optimal true hssi_refclk_divider_powerdown_mode hssi_refclk_divider_powerdown_mode power_off hssi_refclk_divider_sel_pldclk hssi_refclk_divider_sel_pldclk iqclk_sel_lvpecl hssi_refclk_divider_sup_mode hssi_refclk_divider_sup_mode sup_off hssi_refclk_divider_term_tristate hssi_refclk_divider_term_tristate tristate_off hssi_refclk_divider_vcm_pup hssi_refclk_divider_vcm_pup pup_on hssi_refclk_divider_silicon_rev hssi_refclk_divider_silicon_rev 14nm5bcr2eb enable_advanced_options enable_advanced_options 0 enable_hip_options enable_hip_options 0 enable_manual_configuration enable_manual_configuration 1 generate_add_hdl_instance_example Generate '_hw.tcl' 'add_hdl_instance' example file 0 device_family device_family Stratix 10 device device 1SX280HN2F43E2VG base_device base_device Unknown device_die_types device_die_types HSSI_CRETE2E,MAIN_ND5 device_die_revisions device_die_revisions HSSI_CRETE2E_REVB,MAIN_ND5_REVC test_mode Enable Test Mode 0 enable_pld_atx_cal_busy_port enable_pld_atx_cal_busy_port 1 enable_debug_ports_parameters Enable debug ports & parameters 0 support_mode Support mode user_mode message_level Message level for rule violations error pma_speedgrade pma_speedgrade e2 device_revision device_revision 14nm5bcr2eb prot_mode Protocol mode Basic prot_mode_fnl prot_mode_fnl basic_tx primary_use primary_use hssi_hf bw_sel Bandwidth high bw_sel_fnl bw_sel_fnl high_bw refclk_cnt Number of PLL reference clocks 1 refclk_index Selected reference clock source 0 silicon_rev Silicon revision ES false primary_pll_buffer Primary PLL clock output buffer GXT clock output buffer enable_8G_buffer_fnl enable_8G_buffer_fnl false enable_28G_buffer_fnl enable_28G_buffer_fnl true enable_pll_lock Enable ATX PLL lock output port 1 enable_8G_path Enable GX clock output port (tx_serial_clk) 0 enable_28G_output_frm_abv_atx Enable GXT clock output port to above ATX PLL (gxt_output_to_abv_atx) 0 enable_28G_output_frm_blw_atx Enable GXT clock output port to below ATX PLL (gxt_output_to_blw_atx) 0 enable_28G_local_atx_path Enable GXT local clock output port (tx_serial_clk_gxt) 1 enable_28G_input_frm_abv_atx Enable GXT clock input port from above ATX PLL (gxt_input_from_abv_atx) 0 enable_28G_input_frm_blw_atx Enable GXT clock input port from below ATX PLL (gxt_input_from_blw_atx) 0 enable_GXT_out_buffer_abv Enable GXT clock buffer to above ATX PLL 0 enable_GXT_out_buffer_blw Enable GXT clock buffer to below ATX PLL 0 enable_GXT_clock_source GXT output clock source disabled fb_select_fnl fb_select_fnl direct_fb enable_pcie_clk Enable PCIe clock output port 0 enable_cascade_out Enable cascade clock output port 0 enable_atx_to_fpll_cascade_out Enable ATX to FPLL cascade clock output port 0 enable_hip_cal_done_port Enable calibration status ports for HIP 0 set_hip_cal_en Enable PCIe hard IP calibration 0 hip_cal_en hip_cal_en disable dsm_mode dsm_mode dsm_mode_integer set_output_clock_frequency PLL output frequency 12890.625 output_clock_datarate PLL output datarate 25781.25 output_clock_frequency PLL output frequency 12890.625 MHz vco_freq vco_freq 12890.625 MHz datarate datarate 25781.25 Mbps enable_fractional enable_fractional 0 set_auto_reference_clock_frequency PLL auto mode reference clock frequency (Integer) 644.53125 set_manual_reference_clock_frequency PLL manual mode reference clock frequency 200.0 reference_clock_frequency_fnl reference_clock_frequency_fnl 644.531250 set_fref_clock_frequency PLL auto mode reference clock frequency (Fractional) 156.25 feedback_clock_frequency_fnl External feedback frequency 156.25 select_manual_config Configure counters manually false m_counter Multiply factor (M-Counter) 10 effective_m_counter Effective M-Counter 1 set_m_counter Multiply factor (M-Counter) 24 ref_clk_div Divide factor (N-Counter) 1 set_ref_clk_div Divide factor (N-Counter) 1 l_counter Divide factor (L-Counter) 1 set_l_counter Divide factor (L-Counter) 4 l_cascade_counter Divide factor (L-Cascade Counter) 0 set_l_cascade_counter Divide factor (L-Cascade Counter) 4 l_cascade_predivider Divide factor (L-Cascade-Predivider) 1 set_l_cascade_predivider Divide factor (L-Cascade-Predivider) 1 k_counter Fractional multiply factor (K) 1 set_k_counter Fractional multiply factor (K) 1 auto_list auto_list 61.974159 {m 104 effective_m 104 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 62.575850 {m 103 effective_m 103 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 63.189338 {m 102 effective_m 102 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 63.814975 {m 101 effective_m 101 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 64.453125 {m 100 effective_m 100 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 65.104167 {m 99 effective_m 99 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 65.768495 {m 98 effective_m 98 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 66.446521 {m 97 effective_m 97 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 67.138672 {m 96 effective_m 96 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 67.845395 {m 95 effective_m 95 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 68.567154 {m 94 effective_m 94 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 69.304435 {m 93 effective_m 93 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 70.057745 {m 92 effective_m 92 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 70.827610 {m 91 effective_m 91 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 71.614583 {m 90 effective_m 90 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 72.419242 {m 89 effective_m 89 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 73.242188 {m 88 effective_m 88 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 74.084052 {m 87 effective_m 87 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 74.945494 {m 86 effective_m 86 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 75.827206 {m 85 effective_m 85 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 76.729911 {m 84 effective_m 84 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 77.654367 {m 83 effective_m 83 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 78.601372 {m 82 effective_m 82 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 79.571759 {m 81 effective_m 81 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 80.566406 {m 80 effective_m 80 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 81.586234 {m 79 effective_m 79 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 82.632212 {m 78 effective_m 78 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 83.705357 {m 77 effective_m 77 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 84.806743 {m 76 effective_m 76 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 85.937500 {m 75 effective_m 75 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 87.098818 {m 74 effective_m 74 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 88.291952 {m 73 effective_m 73 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 89.518229 {m 72 effective_m 72 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 90.779049 {m 71 effective_m 71 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 92.075893 {m 70 effective_m 70 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 93.410326 {m 69 effective_m 69 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 94.784007 {m 68 effective_m 68 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 96.198694 {m 67 effective_m 67 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 97.656250 {m 66 effective_m 66 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 99.158654 {m 65 effective_m 65 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 100.708008 {m 64 effective_m 64 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 102.306548 {m 63 effective_m 63 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 103.956653 {m 62 effective_m 62 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 105.660861 {m 61 effective_m 61 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 107.421875 {m 60 effective_m 60 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 109.242585 {m 59 effective_m 59 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 111.126078 {m 58 effective_m 58 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 113.075658 {m 57 effective_m 57 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 115.094866 {m 56 effective_m 56 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 117.187500 {m 55 effective_m 55 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 119.357639 {m 54 effective_m 54 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 121.609670 {m 53 effective_m 53 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 123.948317 {m 52 effective_m 52 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 125.151699 {m 103 effective_m 103 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 126.378676 {m 51 effective_m 51 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 127.629950 {m 101 effective_m 101 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 128.906250 {m 50 effective_m 50 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 130.208333 {m 99 effective_m 99 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 131.536990 {m 49 effective_m 49 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 132.893041 {m 97 effective_m 97 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 134.277344 {m 48 effective_m 48 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 135.690789 {m 95 effective_m 95 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 137.134309 {m 47 effective_m 47 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 138.608871 {m 93 effective_m 93 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 140.115489 {m 46 effective_m 46 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 141.655220 {m 91 effective_m 91 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 143.229167 {m 45 effective_m 45 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 144.838483 {m 89 effective_m 89 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 146.484375 {m 44 effective_m 44 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 148.168103 {m 87 effective_m 87 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 149.890988 {m 43 effective_m 43 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 151.654412 {m 85 effective_m 85 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 153.459821 {m 42 effective_m 42 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 155.308735 {m 83 effective_m 83 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 157.202744 {m 41 effective_m 41 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 159.143519 {m 81 effective_m 81 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 161.132812 {m 40 effective_m 40 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 163.172468 {m 79 effective_m 79 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 165.264423 {m 39 effective_m 39 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 167.410714 {m 77 effective_m 77 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 169.613487 {m 38 effective_m 38 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 171.875000 {m 75 effective_m 75 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 174.197635 {m 37 effective_m 37 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 176.583904 {m 73 effective_m 73 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 179.036458 {m 36 effective_m 36 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 181.558099 {m 71 effective_m 71 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 184.151786 {m 35 effective_m 35 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 186.820652 {m 69 effective_m 69 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 189.568015 {m 34 effective_m 34 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 192.397388 {m 67 effective_m 67 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 195.312500 {m 33 effective_m 33 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 198.317308 {m 65 effective_m 65 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 201.416016 {m 32 effective_m 32 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 204.613095 {m 63 effective_m 63 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 207.913306 {m 31 effective_m 31 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 211.321721 {m 61 effective_m 61 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 214.843750 {m 30 effective_m 30 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 218.485169 {m 59 effective_m 59 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 222.252155 {m 29 effective_m 29 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 226.151316 {m 57 effective_m 57 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 230.189732 {m 28 effective_m 28 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 234.375000 {m 55 effective_m 55 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 238.715278 {m 27 effective_m 27 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 243.219340 {m 53 effective_m 53 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 247.896635 {m 26 effective_m 26 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 250.303398 {m 103 effective_m 103 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 252.757353 {m 51 effective_m 51 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 255.259901 {m 101 effective_m 101 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 257.812500 {m 25 effective_m 25 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 260.416667 {m 99 effective_m 99 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 263.073980 {m 49 effective_m 49 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 265.786082 {m 97 effective_m 97 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 268.554688 {m 24 effective_m 24 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 271.381579 {m 95 effective_m 95 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 274.268617 {m 47 effective_m 47 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 277.217742 {m 93 effective_m 93 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 280.230978 {m 23 effective_m 23 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 283.310440 {m 91 effective_m 91 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 286.458333 {m 45 effective_m 45 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 289.676966 {m 89 effective_m 89 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 292.968750 {m 22 effective_m 22 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 296.336207 {m 87 effective_m 87 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 299.781977 {m 43 effective_m 43 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 303.308824 {m 85 effective_m 85 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 306.919643 {m 21 effective_m 21 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 310.617470 {m 83 effective_m 83 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 314.405488 {m 41 effective_m 41 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 318.287037 {m 81 effective_m 81 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 322.265625 {m 20 effective_m 20 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 326.344937 {m 79 effective_m 79 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 330.528846 {m 39 effective_m 39 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 334.821429 {m 77 effective_m 77 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 339.226974 {m 19 effective_m 19 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 343.750000 {m 75 effective_m 75 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 348.395270 {m 37 effective_m 37 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 353.167808 {m 73 effective_m 73 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 358.072917 {m 18 effective_m 18 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 363.116197 {m 71 effective_m 71 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 368.303571 {m 35 effective_m 35 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 373.641304 {m 69 effective_m 69 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 379.136029 {m 17 effective_m 17 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 384.794776 {m 67 effective_m 67 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 390.625000 {m 33 effective_m 33 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 396.634615 {m 65 effective_m 65 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 402.832031 {m 16 effective_m 16 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 409.226190 {m 63 effective_m 63 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 415.826613 {m 31 effective_m 31 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 422.643443 {m 61 effective_m 61 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 429.687500 {m 15 effective_m 15 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 436.970339 {m 59 effective_m 59 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 444.504310 {m 29 effective_m 29 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 452.302632 {m 57 effective_m 57 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 460.379464 {m 14 effective_m 14 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 468.750000 {m 55 effective_m 55 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 477.430556 {m 27 effective_m 27 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 486.438679 {m 53 effective_m 53 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 495.793269 {m 13 effective_m 13 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 500.606796 {m 103 effective_m 103 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 505.514706 {m 51 effective_m 51 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 510.519802 {m 101 effective_m 101 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 515.625000 {m 25 effective_m 25 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 520.833333 {m 99 effective_m 99 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 526.147959 {m 49 effective_m 49 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 531.572165 {m 97 effective_m 97 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 537.109375 {m 12 effective_m 12 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 542.763158 {m 95 effective_m 95 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 548.537234 {m 47 effective_m 47 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 554.435484 {m 93 effective_m 93 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 560.461957 {m 23 effective_m 23 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 566.620879 {m 91 effective_m 91 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 572.916667 {m 45 effective_m 45 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 579.353933 {m 89 effective_m 89 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 585.937500 {m 11 effective_m 11 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 592.672414 {m 87 effective_m 87 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 599.563953 {m 43 effective_m 43 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 606.617647 {m 85 effective_m 85 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 613.839286 {m 21 effective_m 21 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 621.234940 {m 83 effective_m 83 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 628.810976 {m 41 effective_m 41 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 636.574074 {m 81 effective_m 81 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 644.531250 {m 10 effective_m 10 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 652.689873 {m 79 effective_m 79 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 661.057692 {m 39 effective_m 39 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 669.642857 {m 77 effective_m 77 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 678.453947 {m 19 effective_m 19 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 687.500000 {m 75 effective_m 75 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 696.790541 {m 37 effective_m 37 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 706.335616 {m 73 effective_m 73 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 716.145833 {m 9 effective_m 9 n 1 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 726.232394 {m 71 effective_m 71 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 736.607143 {m 35 effective_m 35 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 747.282609 {m 69 effective_m 69 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 758.272059 {m 17 effective_m 17 n 2 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 769.589552 {m 67 effective_m 67 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 781.250000 {m 33 effective_m 33 n 4 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} 793.269231 {m 65 effective_m 65 n 8 l 1 l_cascade 0 l_cascade_predivider 1 k 1 tank_sel lctank0 tank_band lc_band0} manual_list manual_list pll_setting pll_setting refclk 644.531250 m_cnt 10 n_cnt 1 l_cnt 1 k_cnt 1 l_cascade 0 l_cascade_predivider 1 outclk {12890.625 MHz} enable_fb_comp_bonding_fnl enable_fb_comp_bonding_fnl 0 check_output_ports_pll check_output_ports_pll 0 iqclk_sel iqclk_sel iqtxrxclk0 set_altera_xcvr_atx_pll_s10_calibration_en Enable calibration 1 calibration_en calibration_en enable enable_analog_resets Enable pll_powerdown and mcgb_rst ports 0 enable_ext_lockdetect_ports Enable clklow and fref ports 0 enable_debug_options enable_debug_options 0 enable_vco_bypass Enable VCO Bypass feature 0 enable_pcie_hip_connectivity enable_pcie_hip_connectivity 0 usr_analog_voltage VCCR_GXB and VCCT_GXB supply voltage for the Transceiver 1_0V power_mode power_mode mid_power in_pcie_hip_mode in_pcie_hip_mode 0 lc_refclk_select lc_refclk_select 0 enable_mcgb Include Master Clock Generation Block 0 mcgb_div Clock division factor 1 mcgb_div_fnl mcgb_div_fnl 1 enable_hfreq_clk Enable x24 non-bonded high-speed clock output port 0 enable_mcgb_pcie_clksw Enable PCIe clock switch interface 0 enable_mcgb_reset Enable mcgb_rst and mcgb_rst_stat ports 0 mcgb_aux_clkin_cnt Number of auxiliary MCGB clock input ports. 0 mcgb_in_clk_freq MCGB input clock frequency 12890.625 mcgb_out_datarate MCGB output data rate 25781.25 enable_bonding_clks Enable bonding clock output ports 0 enable_fb_comp_bonding Enable feedback compensation bonding 0 mcgb_enable_iqtxrxclk mcgb_enable_iqtxrxclk disable_iqtxrxclk pma_width PMA interface width 64 enable_mcgb_debug_ports_parameters enable_mcgb_debug_ports_parameters 0 enable_pld_mcgb_cal_busy_port enable_pld_mcgb_cal_busy_port 0 check_output_ports_mcgb check_output_ports_mcgb 0 is_protocol_PCIe is_protocol_PCIe 0 mapped_output_clock_frequency mapped_output_clock_frequency 12890.625 MHz mapped_primary_pll_buffer mapped_primary_pll_buffer GXT clock output buffer mapped_hip_cal_done_port mapped_hip_cal_done_port 0 hssi_pma_cgb_master_prot_mode hssi_pma_cgb_master_prot_mode basic_tx hssi_pma_cgb_master_silicon_rev hssi_pma_cgb_master_silicon_rev 14nm5bcr2eb hssi_pma_cgb_master_x1_div_m_sel hssi_pma_cgb_master_x1_div_m_sel divbypass hssi_pma_cgb_master_cgb_enable_iqtxrxclk hssi_pma_cgb_master_cgb_enable_iqtxrxclk disable_iqtxrxclk hssi_pma_cgb_master_ser_mode hssi_pma_cgb_master_ser_mode sixty_four_bit hssi_pma_cgb_master_datarate_bps hssi_pma_cgb_master_datarate_bps 25781250000 hssi_pma_cgb_master_cgb_power_down hssi_pma_cgb_master_cgb_power_down normal_cgb hssi_pma_cgb_master_observe_cgb_clocks hssi_pma_cgb_master_observe_cgb_clocks observe_nothing hssi_pma_cgb_master_tx_ucontrol_reset_pcie hssi_pma_cgb_master_tx_ucontrol_reset_pcie pcscorehip_controls_mcgb hssi_pma_cgb_master_vccdreg_output hssi_pma_cgb_master_vccdreg_output vccdreg_nominal hssi_pma_cgb_master_input_select hssi_pma_cgb_master_input_select lcpll_top hssi_pma_cgb_master_input_select_gen3 hssi_pma_cgb_master_input_select_gen3 not_used gui_parameter_list Parameter Names L cascade predivider/VCO divider(valid in cascade mode) ,L counter (valid in non-cascade mode),L cascade counter (valid in cascade mode),M counter,K counter (valid in fractional mode),N counter,PLL output frequency,vco_freq,datarate gui_parameter_values Parameter Values select_vco_output,1,0,10,1,1,12890.625 MHz,12890.625 MHz,25781.25 Mbps device Device 1SX280HN2F43E2VG deviceFamily Device family Stratix 10 deviceSpeedGrade Device Speed Grade 2 generationId Generation Id 0 bonusData bonusData bonusData { element xcvr_atx_pll_s10_htile_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> false false