// ---------------------------------------------------------------------- // "THE BEER-WARE LICENSE" (Revision 42): // wrote this file. As long as you retain this // notice you can do whatever you want with this stuff. If we meet // some day, and you think this stuff is worth it, you can buy me a // beer in return Yasunori Osana at University of the Ryukyus, // Japan. // ---------------------------------------------------------------------- // OpenFC project: an open FPGA accelerated cluster toolkit // Kyokko project: an open Multi-vendor Aurora 64B/66B-compatible link // // Modules in this file: // a10_xcvr_cb4: Channel-bonded Quad Arria 10 GX transceiver wrapper // c10_phy_bitorder: Bit order reverser for Intel GX transceivers // ---------------------------------------------------------------------- `default_nettype none module a10_xcvr_cb4 # ( parameter NumCh=4 ) ( input wire RST, // RST somehow input wire USRCLK, // 125MHz on HawkEye input wire REFCLK644P, input wire [NumCh-1:0] SFP_RXP, output wire [NumCh-1:0] SFP_TXP, input wire [NumCh*64-1:0] TX_DATA, output wire [NumCh*64-1:0] RX_DATA, input wire [NumCh*2-1:0] TX_CTRL, output wire [NumCh*2-1:0] RX_CTRL, output wire TX_USRCLK, RX_USRCLK, input wire [NumCh-1:0] TX_VALID, RX_BITSLIP, output wire PLL_LOCKED, output wire [NumCh-1:0] RX_LOCKED ); wire PLL_PD; wire TX_SCLK; wire [5:0] TX_BONDING_CLK; atx_5g_4cb atxpll ( .pll_powerdown (PLL_PD), // I .pll_refclk0 (REFCLK644P), // I .tx_serial_clk (TX_SCLK), // O .pll_locked (PLL_LOCKED), // O .pll_cal_busy (), // O .tx_bonding_clocks (TX_BONDING_CLK) ); // O [5:0] wire [NumCh-1:0] TX_ARST, TX_DRST, RX_ARST, RX_DRST; wire [NumCh-1:0] TX_CALBUSY, TX_READY; wire [NumCh-1:0] RX_CALBUSY, RX_READY; phy_rst_ctrl_4ch phy_rst ( .clock (USRCLK), // I .reset (RST), // I .pll_powerdown (PLL_PD), // O .tx_analogreset (TX_ARST), // O [NumCh-1:0] .tx_digitalreset (TX_DRST), // O [NumCh-1:0] .tx_ready (TX_READY), // O [NumCh-1:0] .pll_locked (PLL_LOCKED), // I .pll_select (1'b0), // I .tx_cal_busy (TX_CALBUSY), // I [NumCh-1:0] .rx_analogreset (RX_ARST), // O [NumCh-1:0] .rx_digitalreset (RX_DRST), // O [NumCh-1:0] .rx_ready (RX_READY), // O [NumCh-1:0] .rx_is_lockedtodata (RX_LOCKED), // I [NumCh-1:0] .rx_cal_busy (RX_CALBUSY) // I [NumCh-1:0] ); wire [NumCh-1:0][63:0] RX_DATAi, TX_DATAi; wire [NumCh-1:0][1:0] RX_CTRLi, TX_CTRLi; phy_10g_4cb phy0 ( .tx_analogreset (TX_ARST), // I [4] .tx_digitalreset (TX_DRST), // I [4] .rx_analogreset (RX_ARST), // I [4] .rx_digitalreset (RX_DRST), // I [4] .tx_cal_busy (TX_CALBUSY), // O [4] .rx_cal_busy (RX_CALBUSY), // O [4] .tx_bonding_clocks ({NumCh{TX_BONDING_CLK}}), // O [24] .rx_cdr_refclk0 (REFCLK644P), // I [1] .tx_serial_data (SFP_TXP), // O [4] .rx_serial_data (SFP_RXP), // I [4] .rx_is_lockedtoref (), // O [4] .rx_is_lockedtodata (RX_LOCKED), // O [4] .tx_coreclkin ({NumCh{TX_USRCLK}}), // I [4] .rx_coreclkin ({NumCh{RX_USRCLK}}), // I [4] .tx_clkout (), // O [4] .rx_clkout (), // O [4] .tx_pma_div_clkout (TX_USRCLK), // O [4] .rx_pma_div_clkout (RX_USRCLK), // O [4] .tx_parallel_data (TX_DATAi), // I [256] .tx_control (TX_CTRLi), // I [8] .unused_tx_parallel_data (), // I [256] .unused_tx_control (), // I [64] .rx_parallel_data (RX_DATAi), // O [256] .rx_control (RX_CTRLi), // O [8] .unused_rx_parallel_data (), // O [256] .unused_rx_control (), // O [72] .rx_bitslip (RX_BITSLIP), // I [4] .tx_enh_data_valid ({NumCh{TX_VALID[0]}}), // I [4] .tx_enh_fifo_full (), // O [4] .tx_enh_fifo_empty (), // O [4] .rx_enh_fifo_rd_en ({NumCh{1'b1}}), // I [4] .rx_enh_data_valid (), // O [4] .rx_enh_fifo_full (), // O [4] .rx_enh_fifo_empty () // O [4] ); generate genvar ch; for (ch=0; ch