set_global_assignment -name TOP_LEVEL_ENTITY ip_management
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:44:36  7月 20, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Pro Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name DEVICE 10AX048E4F29E3SG
set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name IP_FILE vio.ip
set_global_assignment -name IP_FILE ila.ip
set_global_assignment -name IP_FILE atx_5g.ip
set_global_assignment -name IP_FILE phy_rst_ctrl_4ch.ip
set_global_assignment -name IP_FILE phy_10g.ip
set_global_assignment -name IP_FILE phy_10g_4cb.ip
set_global_assignment -name IP_FILE atx_5g_4cb.ip