Intel Corporation atx_5g xcvr_atx_pll_a10_0 19.1 pll_powerdown pll_powerdown pll_powerdown associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input pll_refclk0 clk pll_refclk0 clockRate Clock rate 0 externallyDriven Externally driven false ptfSchematicName PTF schematic name ui.blockdiagram.direction input tx_serial_clk clk tx_serial_clk clockRate Clock rate 0 ui.blockdiagram.direction output pll_locked pll_locked pll_locked associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output pll_cal_busy pll_cal_busy pll_cal_busy associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH altera_xcvr_atx_pll_a10 QUARTUS_SYNTH pll_powerdown in STD_LOGIC QUARTUS_SYNTH pll_refclk0 in STD_LOGIC QUARTUS_SYNTH tx_serial_clk out STD_LOGIC QUARTUS_SYNTH pll_locked out STD_LOGIC QUARTUS_SYNTH pll_cal_busy out STD_LOGIC QUARTUS_SYNTH Intel Corporation atx_5g altera_xcvr_atx_pll_a10 19.1 rcfg_debug rcfg_debug 0 enable_pll_reconfig Enable dynamic reconfiguration 0 enable_advanced_avmm_options enable_advanced_avmm_options 0 rcfg_jtag_enable Enable Native PHY Debug Master Endpoint 0 rcfg_separate_avmm_busy Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE 0 rcfg_enable_avmm_busy_port Enable avmm_busy port 0 set_capability_reg_enable Enable capability registers 0 set_user_identifier Set user-defined IP identifier 0 set_csr_soft_logic_enable Enable control and status registers 0 dbg_embedded_debug_enable dbg_embedded_debug_enable 0 dbg_capability_reg_enable dbg_capability_reg_enable 0 dbg_user_identifier dbg_user_identifier 0 dbg_stat_soft_logic_enable dbg_stat_soft_logic_enable 0 dbg_ctrl_soft_logic_enable dbg_ctrl_soft_logic_enable 0 rcfg_file_prefix Configuration file prefix altera_xcvr_atx_pll_a10 rcfg_sv_file_enable Generate SystemVerilog package file 0 rcfg_h_file_enable Generate C header file 0 rcfg_txt_file_enable Generate text file 0 rcfg_mif_file_enable Generate MIF (Memory Initialize File) 0 rcfg_multi_enable Enable multiple reconfiguration profiles 0 set_rcfg_emb_strm_enable Enable embedded reconfiguration streamer 0 rcfg_emb_strm_enable rcfg_emb_strm_enable 0 rcfg_reduced_files_enable Generate reduced reconfiguration files 0 rcfg_profile_cnt Number of reconfiguration profiles 2 rcfg_profile_select Store current configuration to profile: 1 rcfg_profile_data0 rcfg_profile_data0 rcfg_profile_data1 rcfg_profile_data1 rcfg_profile_data2 rcfg_profile_data2 rcfg_profile_data3 rcfg_profile_data3 rcfg_profile_data4 rcfg_profile_data4 rcfg_profile_data5 rcfg_profile_data5 rcfg_profile_data6 rcfg_profile_data6 rcfg_profile_data7 rcfg_profile_data7 rcfg_params rcfg_params rcfg_debug,enable_pll_reconfig,rcfg_jtag_enable,rcfg_separate_avmm_busy,rcfg_enable_avmm_busy_port,set_capability_reg_enable,set_user_identifier,set_csr_soft_logic_enable,enable_pld_atx_cal_busy_port,support_mode,prot_mode,bw_sel,refclk_cnt,refclk_index,primary_pll_buffer,enable_8G_path,enable_16G_path,enable_pcie_clk,enable_cascade_out,enable_hip_cal_done_port,set_hip_cal_en,set_output_clock_frequency,set_auto_reference_clock_frequency,set_manual_reference_clock_frequency,set_fref_clock_frequency,set_m_counter,set_ref_clk_div,set_l_counter,set_l_cascade_counter,set_l_cascade_predivider,set_k_counter,enable_mcgb,mcgb_div,enable_hfreq_clk,enable_mcgb_pcie_clksw,mcgb_aux_clkin_cnt,enable_bonding_clks,enable_fb_comp_bonding,pma_width,enable_pld_mcgb_cal_busy_port rcfg_param_labels IP Parameters rcfg_debug,Enable dynamic reconfiguration,Enable Native PHY Debug Master Endpoint,Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE,Enable avmm_busy port,Enable capability registers,Set user-defined IP identifier,Enable control and status registers,enable_pld_atx_cal_busy_port,Support mode,Protocol mode,Bandwidth,Number of PLL reference clocks,Selected reference clock source,Primary PLL clock output buffer,Enable PLL GX clock output port,Enable PLL GT clock output port,Enable PCIe clock output port,Enable cascade clock output port,Enable calibration status ports for HIP,Enable PCIe hard IP calibration,PLL output frequency,PLL integer reference clock frequency,PLL fractional reference clock frequency,PLL fractional reference clock frequency,Multiply factor (M-Counter),Divide factor (N-Counter),Divide factor (L-Counter),Divide factor (L-Cascade Counter),predivide factor (L-Cascade Predivider),Fractional multiply factor (K),Include Master Clock Generation Block,Clock division factor,Enable x6/xN non-bonded high-speed clock output port,Enable PCIe clock switch interface,Number of auxiliary MCGB clock input ports.,Enable bonding clock output ports,Enable feedback compensation bonding,PMA interface width,enable_pld_mcgb_cal_busy_port rcfg_param_vals0 Profile 0 rcfg_param_vals1 Profile 1 rcfg_param_vals2 Profile 2 rcfg_param_vals3 Profile 3 rcfg_param_vals4 Profile 4 rcfg_param_vals5 Profile 5 rcfg_param_vals6 Profile 6 rcfg_param_vals7 Profile 7 hssi_pma_lc_refclk_select_mux_powerdown_mode hssi_pma_lc_refclk_select_mux_powerdown_mode powerup hssi_pma_lc_refclk_select_mux_xmux_lc_scratch0_src hssi_pma_lc_refclk_select_mux_xmux_lc_scratch0_src scratch0_src_lvpecl hssi_pma_lc_refclk_select_mux_xmux_lc_scratch1_src hssi_pma_lc_refclk_select_mux_xmux_lc_scratch1_src scratch1_src_lvpecl hssi_pma_lc_refclk_select_mux_xmux_lc_scratch2_src hssi_pma_lc_refclk_select_mux_xmux_lc_scratch2_src scratch2_src_lvpecl hssi_pma_lc_refclk_select_mux_xmux_lc_scratch3_src hssi_pma_lc_refclk_select_mux_xmux_lc_scratch3_src scratch3_src_lvpecl hssi_pma_lc_refclk_select_mux_xmux_lc_scratch4_src hssi_pma_lc_refclk_select_mux_xmux_lc_scratch4_src scratch4_src_lvpecl hssi_pma_lc_refclk_select_mux_xmux_refclk_src hssi_pma_lc_refclk_select_mux_xmux_refclk_src src_lvpecl hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_iqclk_sel hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_iqclk_sel power_down hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch0_src hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch0_src scratch0_power_down hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch1_src hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch1_src scratch1_power_down hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch2_src hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch2_src scratch2_power_down hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch3_src hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch3_src scratch3_power_down hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch4_src hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch4_src scratch4_power_down hssi_pma_lc_refclk_select_mux_refclk_select hssi_pma_lc_refclk_select_mux_refclk_select ref_iqclk0 hssi_pma_lc_refclk_select_mux_silicon_rev hssi_pma_lc_refclk_select_mux_silicon_rev 20nm3 hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping ref_iqclk0 hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping power_down hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping power_down hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping power_down hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping power_down hssi_refclk_divider_silicon_rev hssi_refclk_divider_silicon_rev 20nm3 hssi_refclk_divider_clk_divider hssi_refclk_divider_clk_divider div2_off hssi_refclk_divider_core_clk_lvpecl hssi_refclk_divider_core_clk_lvpecl core_clk_lvpecl_off hssi_refclk_divider_enable_lvpecl hssi_refclk_divider_enable_lvpecl lvpecl_enable hssi_refclk_divider_optimal hssi_refclk_divider_optimal true hssi_refclk_divider_powerdown_mode hssi_refclk_divider_powerdown_mode powerup hssi_refclk_divider_sel_pldclk hssi_refclk_divider_sel_pldclk iqclk_sel_lvpecl hssi_refclk_divider_sup_mode hssi_refclk_divider_sup_mode user_mode hssi_refclk_divider_term_tristate hssi_refclk_divider_term_tristate tristate_off hssi_refclk_divider_vcm_pup hssi_refclk_divider_vcm_pup pup_off hssi_refclk_divider_clkbuf_sel hssi_refclk_divider_clkbuf_sel high_vcm hssi_refclk_divider_iostandard hssi_refclk_divider_iostandard lvpecl atx_pll_silicon_rev atx_pll_silicon_rev 20nm3 atx_pll_is_cascaded_pll atx_pll_is_cascaded_pll false atx_pll_cgb_div atx_pll_cgb_div 1 atx_pll_pma_width atx_pll_pma_width 64 atx_pll_lc_atb atx_pll_lc_atb atb_selectdisable atx_pll_cp_compensation_enable atx_pll_cp_compensation_enable true atx_pll_cp_current_setting atx_pll_cp_current_setting cp_current_setting23 atx_pll_cp_testmode atx_pll_cp_testmode cp_normal atx_pll_cp_lf_3rd_pole_freq atx_pll_cp_lf_3rd_pole_freq lf_3rd_pole_setting1 atx_pll_lf_cbig_size atx_pll_lf_cbig_size lf_cbig_setting4 atx_pll_cp_lf_order atx_pll_cp_lf_order lf_3rd_order atx_pll_lf_resistance atx_pll_lf_resistance lf_setting1 atx_pll_lf_ripplecap atx_pll_lf_ripplecap lf_ripple_cap_0 atx_pll_cal_status atx_pll_cal_status cal_in_progress atx_pll_bonding atx_pll_bonding pll_bonding atx_pll_expected_lc_boost_voltage atx_pll_expected_lc_boost_voltage 0 atx_pll_power_rail_et atx_pll_power_rail_et 950 atx_pll_dprio_lc_vreg_boost_scratch atx_pll_dprio_lc_vreg_boost_scratch 0 atx_pll_dprio_lc_vreg1_boost_scratch atx_pll_dprio_lc_vreg1_boost_scratch 0 atx_pll_dprio_clk_vreg_boost_scratch atx_pll_dprio_clk_vreg_boost_scratch 0 atx_pll_dprio_mcgb_vreg_boost_scratch atx_pll_dprio_mcgb_vreg_boost_scratch 0 atx_pll_dprio_vreg_boost_step_size atx_pll_dprio_vreg_boost_step_size 0 atx_pll_dprio_vreg1_boost_step_size atx_pll_dprio_vreg1_boost_step_size 0 atx_pll_dprio_clk_vreg_boost_step_size atx_pll_dprio_clk_vreg_boost_step_size 0 atx_pll_dprio_mcgb_vreg_boost_step_size atx_pll_dprio_mcgb_vreg_boost_step_size 0 atx_pll_dprio_lc_vreg_boost_expected_voltage atx_pll_dprio_lc_vreg_boost_expected_voltage 0 atx_pll_dprio_lc_vreg1_boost_expected_voltage atx_pll_dprio_lc_vreg1_boost_expected_voltage 0 atx_pll_dprio_clk_vreg_boost_expected_voltage atx_pll_dprio_clk_vreg_boost_expected_voltage 0 atx_pll_dprio_mcgb_vreg_boost_expected_voltage atx_pll_dprio_mcgb_vreg_boost_expected_voltage 0 atx_pll_clk_high_perf_voltage atx_pll_clk_high_perf_voltage 0 atx_pll_clk_mid_power_voltage atx_pll_clk_mid_power_voltage 0 atx_pll_clk_low_power_voltage atx_pll_clk_low_power_voltage 0 atx_pll_tank_sel atx_pll_tank_sel lctank1 atx_pll_tank_band atx_pll_tank_band lc_band4 atx_pll_tank_voltage_coarse atx_pll_tank_voltage_coarse vreg_setting_coarse0 atx_pll_tank_voltage_fine atx_pll_tank_voltage_fine vreg_setting5 atx_pll_output_regulator_supply atx_pll_output_regulator_supply vreg1v_setting0 atx_pll_overrange_voltage atx_pll_overrange_voltage over_setting0 atx_pll_underrange_voltage atx_pll_underrange_voltage under_setting4 atx_pll_fb_select atx_pll_fb_select direct_fb atx_pll_d2a_voltage atx_pll_d2a_voltage d2a_setting_4 atx_pll_dsm_mode atx_pll_dsm_mode dsm_mode_integer atx_pll_dsm_out_sel atx_pll_dsm_out_sel pll_dsm_disable atx_pll_dsm_ecn_bypass atx_pll_dsm_ecn_bypass false atx_pll_dsm_ecn_test_en atx_pll_dsm_ecn_test_en false atx_pll_dsm_fractional_division K counter (valid in fractional mode) 1 atx_pll_dsm_fractional_value_ready atx_pll_dsm_fractional_value_ready pll_k_ready atx_pll_enable_lc_calibration atx_pll_enable_lc_calibration true atx_pll_enable_lc_vreg_calibration atx_pll_enable_lc_vreg_calibration true atx_pll_iqclk_mux_sel atx_pll_iqclk_mux_sel iqtxrxclk0 atx_pll_vco_bypass_enable atx_pll_vco_bypass_enable false atx_pll_l_counter L counter (valid in non-cascade mode) 2 atx_pll_l_counter_enable atx_pll_l_counter_enable true atx_pll_cascadeclk_test atx_pll_cascadeclk_test cascadetest_off atx_pll_hclk_divide atx_pll_hclk_divide 1 atx_pll_enable_hclk atx_pll_enable_hclk hclk_disabled atx_pll_m_counter M counter 16 atx_pll_ref_clk_div N counter 2 atx_pll_bandwidth_range_high atx_pll_bandwidth_range_high 0 hz atx_pll_bandwidth_range_low atx_pll_bandwidth_range_low 0 hz atx_pll_bw_sel atx_pll_bw_sel medium atx_pll_calibration_mode atx_pll_calibration_mode cal_off atx_pll_datarate Datarate 10312500000 bps atx_pll_device_variant atx_pll_device_variant device1 atx_pll_f_max_pfd atx_pll_f_max_pfd 350000000 Hz atx_pll_f_max_ref atx_pll_f_max_ref 800000000 Hz atx_pll_f_max_tank_0 atx_pll_f_max_tank_0 8800000000 Hz atx_pll_f_max_tank_1 atx_pll_f_max_tank_1 11400000000 Hz atx_pll_f_max_tank_2 atx_pll_f_max_tank_2 14400000000 Hz atx_pll_f_max_vco atx_pll_f_max_vco 14400000000 Hz atx_pll_f_max_x1 atx_pll_f_max_x1 8700000000 Hz atx_pll_f_min_pfd atx_pll_f_min_pfd 61440000 Hz atx_pll_f_min_ref atx_pll_f_min_ref 61440000 Hz atx_pll_f_min_tank_0 atx_pll_f_min_tank_0 6500000000 Hz atx_pll_f_min_tank_1 atx_pll_f_min_tank_1 8800000000 Hz atx_pll_f_min_tank_2 atx_pll_f_min_tank_2 11400000000 Hz atx_pll_f_min_vco atx_pll_f_min_vco 7200000000 Hz atx_pll_initial_settings atx_pll_initial_settings true atx_pll_l_counter_scratch atx_pll_l_counter_scratch 1 atx_pll_lc_mode atx_pll_lc_mode lccmu_normal atx_pll_n_counter_scratch atx_pll_n_counter_scratch 1 atx_pll_output_clock_frequency atx_pll_output_clock_frequency 5156250000 Hz atx_pll_power_mode atx_pll_power_mode low_power atx_pll_powerdown_mode atx_pll_powerdown_mode powerup atx_pll_prot_mode atx_pll_prot_mode basic_tx atx_pll_reference_clock_frequency atx_pll_reference_clock_frequency 644531250 Hz atx_pll_side atx_pll_side side_unknown atx_pll_pm_speed_grade atx_pll_pm_speed_grade e4 atx_pll_sup_mode atx_pll_sup_mode user_mode atx_pll_top_or_bottom atx_pll_top_or_bottom tb_unknown atx_pll_vccdreg_clk atx_pll_vccdreg_clk vreg_clk5 atx_pll_vccdreg_fb atx_pll_vccdreg_fb vreg_fb8 atx_pll_vccdreg_fw atx_pll_vccdreg_fw vreg_fw5 atx_pll_regulator_bypass atx_pll_regulator_bypass reg_enable atx_pll_vco_freq VCO Frequency 10312500000 Hz atx_pll_f_max_vco_fractional atx_pll_f_max_vco_fractional 0 hz atx_pll_f_max_pfd_fractional atx_pll_f_max_pfd_fractional 0 hz atx_pll_min_fractional_percentage atx_pll_min_fractional_percentage 0 atx_pll_max_fractional_percentage atx_pll_max_fractional_percentage 100 atx_pll_analog_mode atx_pll_analog_mode user_custom atx_pll_is_otn atx_pll_is_otn false atx_pll_is_sdi atx_pll_is_sdi false atx_pll_primary_use atx_pll_primary_use hssi_x1 atx_pll_fpll_refclk_selection L cascade predivider/VCO divider(valid in cascade mode) select_vco_output atx_pll_lc_to_fpll_l_counter_scratch L cascade counter (valid in cascade mode) 1 atx_pll_lc_to_fpll_l_counter atx_pll_lc_to_fpll_l_counter lcounter_setting0 atx_pll_pfd_delay_compensation atx_pll_pfd_delay_compensation normal_delay atx_pll_xcpvco_xchgpmplf_cp_current_boost atx_pll_xcpvco_xchgpmplf_cp_current_boost normal_setting atx_pll_f_max_lcnt_fpll_cascading atx_pll_f_max_lcnt_fpll_cascading 1200000000 atx_pll_pfd_pulse_width atx_pll_pfd_pulse_width pulse_width_setting0 atx_pll_enable_idle_atx_pll_support atx_pll_enable_idle_atx_pll_support idle_none enable_advanced_options enable_advanced_options 0 enable_hip_options enable_hip_options 0 enable_manual_configuration enable_manual_configuration 1 generate_docs Generate parameter documentation file 0 generate_add_hdl_instance_example Generate '_hw.tcl' 'add_hdl_instance' example file 0 device_family device_family Arria 10 device device 10AX048E4F29E3SG base_device base_device NIGHTFURY3 test_mode Enable Test Mode 0 enable_pld_atx_cal_busy_port enable_pld_atx_cal_busy_port 1 enable_debug_ports_parameters Enable debug ports & parameters 0 support_mode Support mode user_mode message_level Message level for rule violations error pma_speedgrade pma_speedgrade e4 device_revision device_revision 20nm3 prot_mode Protocol mode Basic prot_mode_fnl prot_mode_fnl basic_tx primary_use primary_use hssi_x1 bw_sel Bandwidth medium refclk_cnt Number of PLL reference clocks 1 refclk_index Selected reference clock source 0 silicon_rev Silicon revision ES false fb_select_fnl fb_select_fnl direct_fb primary_pll_buffer Primary PLL clock output buffer GX clock output buffer enable_8G_buffer_fnl enable_8G_buffer_fnl true enable_16G_buffer_fnl enable_16G_buffer_fnl false enable_8G_path Enable PLL GX clock output port 1 enable_16G_path Enable PLL GT clock output port 0 enable_pcie_clk Enable PCIe clock output port 0 enable_cascade_out Enable cascade clock output port 0 enable_atx_to_fpll_cascade_out Enable ATX to FPLL cascade clock output port 0 enable_hip_cal_done_port Enable calibration status ports for HIP 0 set_hip_cal_en Enable PCIe hard IP calibration 0 hip_cal_en hip_cal_en disable dsm_mode dsm_mode dsm_mode_integer set_output_clock_frequency PLL output frequency 5156.25 output_clock_datarate PLL output datarate 10312.5 output_clock_frequency PLL output frequency 5156.25 MHz vco_freq vco_freq 10312.5 MHz datarate datarate 10312.5 Mbps enable_fractional enable_fractional 0 set_auto_reference_clock_frequency PLL integer reference clock frequency 644.53125 set_manual_reference_clock_frequency PLL fractional reference clock frequency 200.0 reference_clock_frequency_fnl reference_clock_frequency_fnl 644.531250 MHz set_fref_clock_frequency PLL fractional reference clock frequency 156.25 feedback_clock_frequency_fnl External feedback frequency 156.25 select_manual_config Configure counters manually false m_counter Multiply factor (M-Counter) 16 effective_m_counter Effective M-Counter 1 set_m_counter Multiply factor (M-Counter) 24 ref_clk_div Divide factor (N-Counter) 2 set_ref_clk_div Divide factor (N-Counter) 1 l_counter Divide factor (L-Counter) 2 set_l_counter Divide factor (L-Counter) 16 l_cascade_counter Divide factor (L-Cascade-Counter) 1 set_l_cascade_counter Divide factor (L-Cascade Counter) 15 l_cascade_predivider Divide factor (L-Cascade-Predivider) 1 set_l_cascade_predivider predivide factor (L-Cascade Predivider) 1 k_counter Fractional multiply factor (K) 1 set_k_counter Fractional multiply factor (K) 2000000000 auto_list auto_list 62.123494 {m 83 effective_m 83 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 62.881098 {m 82 effective_m 82 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 63.657407 {m 81 effective_m 81 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 64.453125 {m 80 effective_m 80 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 65.268987 {m 79 effective_m 79 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 66.105769 {m 78 effective_m 78 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 66.964286 {m 77 effective_m 77 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 67.845395 {m 76 effective_m 76 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 68.750000 {m 75 effective_m 75 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 69.679054 {m 74 effective_m 74 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 70.633562 {m 73 effective_m 73 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 71.614583 {m 72 effective_m 72 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 72.623239 {m 71 effective_m 71 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 73.660714 {m 70 effective_m 70 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 74.728261 {m 69 effective_m 69 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 75.827206 {m 68 effective_m 68 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 76.958955 {m 67 effective_m 67 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 78.125000 {m 66 effective_m 66 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 79.326923 {m 65 effective_m 65 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 80.566406 {m 64 effective_m 64 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 81.845238 {m 63 effective_m 63 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 83.165323 {m 62 effective_m 62 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 84.528689 {m 61 effective_m 61 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 85.937500 {m 60 effective_m 60 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 87.394068 {m 59 effective_m 59 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 88.900862 {m 58 effective_m 58 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 90.460526 {m 57 effective_m 57 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 92.075893 {m 56 effective_m 56 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 93.750000 {m 55 effective_m 55 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 95.486111 {m 54 effective_m 54 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 97.287736 {m 53 effective_m 53 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 99.158654 {m 52 effective_m 52 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 101.102941 {m 51 effective_m 51 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 103.125000 {m 50 effective_m 50 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 105.229592 {m 49 effective_m 49 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 107.421875 {m 48 effective_m 48 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 109.707447 {m 47 effective_m 47 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 112.092391 {m 46 effective_m 46 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 114.583333 {m 45 effective_m 45 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 117.187500 {m 44 effective_m 44 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 119.912791 {m 43 effective_m 43 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 122.767857 {m 42 effective_m 42 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 124.246988 {m 83 effective_m 83 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 125.762195 {m 41 effective_m 41 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 127.314815 {m 81 effective_m 81 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 128.906250 {m 40 effective_m 40 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 130.537975 {m 79 effective_m 79 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 132.211538 {m 39 effective_m 39 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 133.928571 {m 77 effective_m 77 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 135.690789 {m 38 effective_m 38 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 137.500000 {m 75 effective_m 75 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 139.358108 {m 37 effective_m 37 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 141.267123 {m 73 effective_m 73 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 143.229167 {m 36 effective_m 36 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 145.246479 {m 71 effective_m 71 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 147.321429 {m 35 effective_m 35 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 149.456522 {m 69 effective_m 69 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 151.654412 {m 34 effective_m 34 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 153.917910 {m 67 effective_m 67 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 156.250000 {m 33 effective_m 33 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 158.653846 {m 65 effective_m 65 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 161.132812 {m 32 effective_m 32 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 163.690476 {m 63 effective_m 63 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 166.330645 {m 31 effective_m 31 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 169.057377 {m 61 effective_m 61 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 171.875000 {m 30 effective_m 30 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 174.788136 {m 59 effective_m 59 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 177.801724 {m 29 effective_m 29 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 180.921053 {m 57 effective_m 57 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 184.151786 {m 28 effective_m 28 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 187.500000 {m 55 effective_m 55 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 190.972222 {m 27 effective_m 27 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 194.575472 {m 53 effective_m 53 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 198.317308 {m 26 effective_m 26 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 202.205882 {m 51 effective_m 51 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 206.250000 {m 25 effective_m 25 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 210.459184 {m 49 effective_m 49 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 214.843750 {m 24 effective_m 24 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 219.414894 {m 47 effective_m 47 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 224.184783 {m 23 effective_m 23 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 229.166667 {m 45 effective_m 45 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 234.375000 {m 22 effective_m 22 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 239.825581 {m 43 effective_m 43 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 245.535714 {m 21 effective_m 21 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 248.493976 {m 83 effective_m 83 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 251.524390 {m 41 effective_m 41 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 254.629630 {m 81 effective_m 81 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 257.812500 {m 20 effective_m 20 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 261.075949 {m 79 effective_m 79 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 264.423077 {m 39 effective_m 39 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 267.857143 {m 77 effective_m 77 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 271.381579 {m 19 effective_m 19 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 275.000000 {m 75 effective_m 75 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 278.716216 {m 37 effective_m 37 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 282.534247 {m 73 effective_m 73 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 286.458333 {m 18 effective_m 18 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 290.492958 {m 71 effective_m 71 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 294.642857 {m 35 effective_m 35 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 298.913043 {m 69 effective_m 69 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 303.308824 {m 17 effective_m 17 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 307.835821 {m 67 effective_m 67 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 312.500000 {m 33 effective_m 33 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 317.307692 {m 65 effective_m 65 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 322.265625 {m 16 effective_m 16 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 327.380952 {m 63 effective_m 63 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 332.661290 {m 31 effective_m 31 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 338.114754 {m 61 effective_m 61 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 343.750000 {m 15 effective_m 15 n 1 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 349.576271 {m 59 effective_m 59 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 355.603448 {m 29 effective_m 29 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 361.842105 {m 57 effective_m 57 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 368.303571 {m 28 effective_m 28 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 375.000000 {m 55 effective_m 55 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 381.944444 {m 27 effective_m 27 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 389.150943 {m 53 effective_m 53 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 396.634615 {m 26 effective_m 26 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 404.411765 {m 51 effective_m 51 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 412.500000 {m 25 effective_m 25 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 420.918367 {m 49 effective_m 49 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 429.687500 {m 24 effective_m 24 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 438.829787 {m 47 effective_m 47 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 448.369565 {m 23 effective_m 23 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 458.333333 {m 45 effective_m 45 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 468.750000 {m 22 effective_m 22 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 479.651163 {m 43 effective_m 43 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 491.071429 {m 21 effective_m 21 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 496.987952 {m 83 effective_m 83 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 503.048780 {m 41 effective_m 41 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 509.259259 {m 81 effective_m 81 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 515.625000 {m 20 effective_m 20 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 522.151899 {m 79 effective_m 79 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 528.846154 {m 39 effective_m 39 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 535.714286 {m 77 effective_m 77 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 542.763158 {m 19 effective_m 19 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 550.000000 {m 75 effective_m 75 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 557.432432 {m 37 effective_m 37 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 565.068493 {m 73 effective_m 73 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 572.916667 {m 18 effective_m 18 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 580.985915 {m 71 effective_m 71 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 589.285714 {m 35 effective_m 35 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 597.826087 {m 69 effective_m 69 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 606.617647 {m 17 effective_m 17 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 615.671642 {m 67 effective_m 67 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 625.000000 {m 33 effective_m 33 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 634.615385 {m 65 effective_m 65 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 644.531250 {m 16 effective_m 16 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 654.761905 {m 63 effective_m 63 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 665.322581 {m 31 effective_m 31 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 676.229508 {m 61 effective_m 61 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 687.500000 {m 15 effective_m 15 n 2 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 699.152542 {m 59 effective_m 59 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 711.206897 {m 29 effective_m 29 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 723.684211 {m 57 effective_m 57 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 736.607143 {m 28 effective_m 28 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 750.000000 {m 55 effective_m 55 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 763.888889 {m 27 effective_m 27 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 778.301887 {m 53 effective_m 53 n 8 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 793.269231 {m 26 effective_m 26 n 4 l 2 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} manual_list manual_list pll_setting pll_setting refclk {644.531250 MHz} m_cnt 16 n_cnt 2 l_cnt 2 k_cnt 1 l_cascade 1 l_cascade_predivider 1 outclk {5156.25 MHz} enable_fb_comp_bonding_fnl enable_fb_comp_bonding_fnl 0 check_output_ports_pll check_output_ports_pll 0 iqclk_mux_sel iqclk_mux_sel iqtxrxclk0 set_altera_xcvr_atx_pll_a10_calibration_en Enable calibration 1 calibration_en calibration_en enable enable_analog_resets Enable pll_powerdown and mcgb_rst connections 0 enable_ext_lockdetect_ports Enable clklow and fref ports 0 is_c10 is_c10 0 atx_pll_bonding_mode atx_pll_bonding_mode cpri_bonding lc_refclk_select lc_refclk_select 0 enable_mcgb Include Master Clock Generation Block 0 mcgb_div Clock division factor 1 mcgb_div_fnl mcgb_div_fnl 1 enable_hfreq_clk Enable x6/xN non-bonded high-speed clock output port 0 enable_mcgb_pcie_clksw Enable PCIe clock switch interface 0 mcgb_aux_clkin_cnt Number of auxiliary MCGB clock input ports. 0 mcgb_in_clk_freq MCGB input clock frequency 5156.25 mcgb_out_datarate MCGB output data rate 10312.5 enable_bonding_clks Enable bonding clock output ports 0 enable_fb_comp_bonding Enable feedback compensation bonding 0 mcgb_enable_iqtxrxclk mcgb_enable_iqtxrxclk disable_iqtxrxclk pma_width PMA interface width 64 enable_mcgb_debug_ports_parameters enable_mcgb_debug_ports_parameters 0 enable_pld_mcgb_cal_busy_port enable_pld_mcgb_cal_busy_port 0 check_output_ports_mcgb check_output_ports_mcgb 0 is_protocol_PCIe is_protocol_PCIe 0 mapped_output_clock_frequency mapped_output_clock_frequency 5156.25 MHz mapped_primary_pll_buffer mapped_primary_pll_buffer GX clock output buffer mapped_hip_cal_done_port mapped_hip_cal_done_port 0 hssi_pma_cgb_master_prot_mode hssi_pma_cgb_master_prot_mode basic_tx hssi_pma_cgb_master_silicon_rev hssi_pma_cgb_master_silicon_rev 20nm3 hssi_pma_cgb_master_x1_div_m_sel hssi_pma_cgb_master_x1_div_m_sel divbypass hssi_pma_cgb_master_cgb_enable_iqtxrxclk hssi_pma_cgb_master_cgb_enable_iqtxrxclk disable_iqtxrxclk hssi_pma_cgb_master_ser_mode hssi_pma_cgb_master_ser_mode sixty_four_bit hssi_pma_cgb_master_datarate hssi_pma_cgb_master_datarate 10312500000 bps hssi_pma_cgb_master_cgb_power_down hssi_pma_cgb_master_cgb_power_down normal_cgb hssi_pma_cgb_master_observe_cgb_clocks hssi_pma_cgb_master_observe_cgb_clocks observe_nothing hssi_pma_cgb_master_op_mode hssi_pma_cgb_master_op_mode enabled hssi_pma_cgb_master_tx_ucontrol_reset_pcie hssi_pma_cgb_master_tx_ucontrol_reset_pcie pcscorehip_controls_mcgb hssi_pma_cgb_master_vccdreg_output hssi_pma_cgb_master_vccdreg_output vccdreg_nominal hssi_pma_cgb_master_input_select hssi_pma_cgb_master_input_select lcpll_top hssi_pma_cgb_master_input_select_gen3 hssi_pma_cgb_master_input_select_gen3 unused gui_parameter_list Parameter Names K counter (valid in fractional mode),L counter (valid in non-cascade mode),M counter,N counter,L cascade predivider/VCO divider(valid in cascade mode) ,L cascade counter (valid in cascade mode),PLL output frequency,vco_freq,datarate gui_parameter_values Parameter Values 1,2,16,2,select_vco_output,1,5156.25 MHz,10312.5 MHz,10312.5 Mbps device Device 10AX048E4F29E3SG deviceFamily Device family Arria 10 deviceSpeedGrade Device Speed Grade 3 generationId Generation Id 0 bonusData bonusData bonusData { element xcvr_atx_pll_a10_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> false false