Intel Corporation vio in_system_sources_probes_0 19.2.0 sources source source associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false probes probe probe associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH altera_in_system_sources_probes QUARTUS_SYNTH source out 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH probe in 0 7 STD_LOGIC_VECTOR QUARTUS_SYNTH Intel Corporation vio altera_in_system_sources_probes 19.2.0 device_family device_family Stratix 10 gui_use_auto_index Automatic Instance Index Assignment true sld_auto_instance_index sld_auto_instance_index YES sld_instance_index Instance Index 0 instance_id The 'Instance ID' of this instance (optional) NONE probe_width Probe Port Width [0..511] 8 source_width Source Port Width [0..511] 8 source_initial_value Hexadecimal initial value for the Source Port 0 create_source_clock Use Source Clock false create_source_clock_enable Use Source Clock Enable false enable_metastability enable_metastability NO embeddedsw.dts.group ignore embeddedsw.dts.name debug embeddedsw.dts.vendor altr device Device 1SG280LU2F50E1VG deviceFamily Device family Stratix 10 deviceSpeedGrade Device Speed Grade 1 generationId Generation Id 0 bonusData bonusData bonusData { element in_system_sources_probes_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> false false