Intel Corporation phy_rst_ctrl_2ch xcvr_reset_control_0 19.1.1 clock clk clock clockRate Clock rate 0 externallyDriven Externally driven false ptfSchematicName PTF schematic name reset reset reset associatedClock Associated clock synchronousEdges Synchronous edges NONE pll_powerdown pll_powerdown pll_powerdown associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_analogreset tx_analogreset tx_analogreset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_digitalreset tx_digitalreset tx_digitalreset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output tx_ready tx_ready tx_ready associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output pll_locked pll_locked pll_locked associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input pll_select pll_select pll_select associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input tx_cal_busy tx_cal_busy tx_cal_busy associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_analogreset rx_analogreset rx_analogreset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_digitalreset rx_digitalreset rx_digitalreset associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_ready rx_ready rx_ready associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction output rx_is_lockedtodata rx_is_lockedtodata rx_is_lockedtodata associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input rx_cal_busy rx_cal_busy rx_cal_busy associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false ui.blockdiagram.direction input QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH altera_xcvr_reset_control QUARTUS_SYNTH clock in STD_LOGIC QUARTUS_SYNTH reset in STD_LOGIC QUARTUS_SYNTH pll_powerdown out STD_LOGIC_VECTOR QUARTUS_SYNTH tx_analogreset out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_digitalreset out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH tx_ready out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH pll_locked in STD_LOGIC_VECTOR QUARTUS_SYNTH pll_select in STD_LOGIC_VECTOR QUARTUS_SYNTH tx_cal_busy in 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_analogreset out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_digitalreset out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_ready out 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_is_lockedtodata in 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH rx_cal_busy in 0 1 STD_LOGIC_VECTOR QUARTUS_SYNTH Intel Corporation phy_rst_ctrl_2ch altera_xcvr_reset_control 19.1.1 device_family device_family Cyclone 10 GX CHANNELS Number of transceiver channels 2 PLLS Number of TX PLLs 1 SYS_CLK_IN_MHZ Input clock frequency 100 SYNCHRONIZE_RESET Synchronize reset input 1 REDUCED_SIM_TIME Use fast reset for simulation 1 gui_split_interfaces Separate interface per channel/PLL 0 TX_PLL_ENABLE Enable TX PLL reset control 1 T_PLL_POWERDOWN pll_powerdown duration 1000 SYNCHRONIZE_PLL_RESET Synchronize reset input for PLL powerdown 0 TX_ENABLE Enable TX channel reset control 1 TX_PER_CHANNEL Use separate TX reset per channel 0 gui_tx_auto_reset TX digital reset mode 0 T_TX_ANALOGRESET tx_analogreset duration 0 T_TX_DIGITALRESET tx_digitalreset duration 20 T_PLL_LOCK_HYST pll_locked input hysteresis 0 gui_pll_cal_busy Enable pll_cal_busy input port 0 RX_ENABLE Enable RX channel reset control 1 RX_PER_CHANNEL Use separate RX reset per channel 1 gui_rx_auto_reset RX digital reset mode 0 T_RX_ANALOGRESET rx_analogreset duration 40 T_RX_DIGITALRESET rx_digitalreset duration 4000 board Board default device Device 10CX220YF780E5G deviceFamily Device family Cyclone 10 GX deviceSpeedGrade Device Speed Grade 5 generationId Generation Id 0 bonusData bonusData bonusData { element xcvr_reset_control_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> false false