Intel Corporation ila signaltap_ii_logic_analyzer_0 19.2.0 tap acq_data_in acq_data_in acq_trigger_in acq_trigger_in associatedClock associatedClock acq_clk associatedReset associatedReset prSafe Partial Reconfiguration Safe false acq_clk clk acq_clk clockRate Clock rate 0 externallyDriven Externally driven false ptfSchematicName PTF schematic name QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH altera_signaltap_ii_logic_analyzer QUARTUS_SYNTH acq_data_in in 0 143 STD_LOGIC_VECTOR QUARTUS_SYNTH acq_trigger_in in STD_LOGIC_VECTOR QUARTUS_SYNTH acq_clk in STD_LOGIC QUARTUS_SYNTH Intel Corporation ila altera_signaltap_ii_logic_analyzer 19.2.0 device_family device_family Cyclone 10 GX SLD_DATA_BITS Data Input Port Width [1..4096] 144 SLD_SAMPLE_DEPTH Sample Depth 1024 gui_ram_type RAM type AUTO SLD_RAM_BLOCK_TYPE SLD_RAM_BLOCK_TYPE AUTO gui_use_segmented Segmented false gui_num_segments Number of Segments 2 gui_sample_per_segment Samples per Segment SLD_SEGMENT_SIZE SLD_SEGMENT_SIZE 0 gui_sq Storage Qualifier Continuous SLD_STORAGE_QUALIFIER_MODE SLD_STORAGE_QUALIFIER_MODE OFF SLD_STORAGE_QUALIFIER_GAP_RECORD Record data discontinuities 0 SLD_TRIGGER_BITS Trigger Input Port Width [1..4096] 1 SLD_TRIGGER_LEVEL Trigger Conditions 1 SLD_TRIGGER_IN_ENABLED Trigger In 0 gui_trigger_out_enabled Trigger Out false SLD_ENABLE_ADVANCED_TRIGGER SLD_ENABLE_ADVANCED_TRIGGER 0 SLD_TRIGGER_LEVEL_PIPELINE SLD_TRIGGER_LEVEL_PIPELINE 1 SLD_PIPELINE_FACTOR Pipeline Factor 4 SLD_TRIGGER_PIPELINE SLD_TRIGGER_PIPELINE 2 SLD_RAM_PIPELINE SLD_RAM_PIPELINE 4 SLD_COUNTER_PIPELINE SLD_COUNTER_PIPELINE 1 SLD_NODE_INFO SLD_NODE_INFO 806383104 SLD_INCREMENTAL_ROUTING SLD_INCREMENTAL_ROUTING 0 SLD_NODE_CRC_BITS SLD_NODE_CRC_BITS 32 SLD_NODE_CRC_HIWORD SLD_NODE_CRC_HIWORD 32769 SLD_NODE_CRC_LOWORD SLD_NODE_CRC_LOWORD 20051 device Device 10CX220YF780E5G deviceFamily Device family Cyclone 10 GX deviceSpeedGrade Device Speed Grade 5 generationId Generation Id 0 bonusData bonusData bonusData { element signaltap_ii_logic_analyzer_0 { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog true lockedInterfaceDefinition lockedInterfaceDefinition systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> false false